Runhao Han’s research while affiliated with Chinese Academy of Sciences and other places

For the first time, we present a one-transistor dynamic random access memory (DRAM) cell using the ferroelectric polarization-assisted charge trapping phenomenon. The gate structure is TiN/Hf _0.5 Zr _0.5 O ₂ /SiO _X /Si substrate. The spontaneous polarization of ferroelectric Hf _0.5 Zr _0.5 O is directed toward the substrate during programming and erasing operations. The purpose of introducing ferroelectric Hf _0.5 Zr _0.5 O ₂ is to induce significant charge trapping. The device utilizes charge trapping for programming and detrapping for erasing. The proposed one-transistor DRAM (1T-DRAM) device shows fast write, latency-free reads, nondestructive readout, and excellent endurance characteristics (>10 ¹⁰ ).

In this work, we propose a gate structure to enhance the memory window (MW) of Si-channel Hf0.5Zr0.5O2 FeFETs. We achieve an MW of 10.04 V by inserting an Al2O3/HfO2/Al2O3 (AHA) top dielectric interlayer between the ferroelectric Hf0.5Zr0.5O2 layer and the metal gate, where the gate-stack thickness is 14.8 nm. The physical origin is that the Al2O3/HfO2, HfO2/Al2O3, and Al2O3/Hf0.5Zr0.5O2 interfaces can trap charges from the metal gate, contributing to the MW enhancement. This AHA top dielectric multilayer effectively suppresses charge loss compared with a single Al2O3 top dielectric interlayer. Moreover, the de-trapping of charges injected from the metal gate is the primary factor for the degradation of the MW in this structure. Our work provides a guide for improving the MW of FeFET.

In this work, we investigate the effect of nitridation of the bottom interlayer in HfO $_{\text{2}}$ -based ferroelectric silicon channel field-effect transistors (HfO $_{\text{2}}$ Si-FeFETs) with the TiN/top interlayer/ferroelectric/bottom interlayer/Si substrate (MIFIS) structure. We find that the SiON bottom interlayer induces a smaller memory window (MW) compared with the case of SiO $_{\text{2}}$ as a bottom interlayer in the MIFIS structure. The origin is the reduced barrier height at the bottom interlayer induced by the positive charges in the SiON layer, which makes the charges injected from the metal gate cannot remain after erasing operation. However, the SiON bottom interface in the MIFIS structure shows higher endurance and stable retention than the SiO $_{\text{2}}$ bottom interface. Thus, for the ferroelectric field-effect transistor (FeFET) gate stacks with a top interlayer (MIFIS structure), the SiO $_{\text{2}}$ is more suitable than the SiON as a bottom interlayer to realize larger MW, while the SiON bottom interlayer can improve retention and endurance at the expense of MW.

We investigate the effect of top Al2O3 interlayer thickness on the memory window (MW) of Si channel ferroelectric field-effect transistors (Si-FeFETs) with TiN/Al2O3/Hf0.5Zr0.5O2/SiOx/Si (MIFIS) gate structure. We find that the MW first increases and then remains almost constant with the increasing thickness of the top Al2O3. The phenomenon is attributed to the lower electric field of the ferroelectric Hf0.5Zr0.5O2 in the MIFIS structure with a thicker top Al2O3 after a program operation. The lower electric field makes the charges trapped at the top Al2O3/Hf0.5Zr0.5O2 interface, which are injected from the metal gate, cannot be retained. Furthermore, we study the effect of the top Al2O3 interlayer thickness on the reliability (endurance characteristics and retention characteristics). We find that the MIFIS structure with a thicker top Al2O3 interlayer has poorer retention and endurance characteristics. Our work is helpful in deeply understanding the effect of top interlayer thickness on the MW and reliability of Si-FeFETs with MIFIS gate stacks.

We study the impact of top SiO2 interlayer thickness on the memory window (MW) of Si channel ferroelectric field-effect transistor (FeFET) with TiN/SiO2/ Hf0.5Zr0.5O2/SiOx/Si (MIFIS) gate structure. We find that the MW increases with the increasing thickness of the top SiO2 interlayer, and such an increase exhibits a two-stage linear dependence. The physical origin is the presence of the different interfacial charges trapped at the top SiO2/Hf0.5Zr0.5O2 interface. Moreover, we investigate the dependence of endurance characteristics on initial MW. We find that the endurance characteristic degrades with increasing the initial MW. Meanwhile, we study the impact of the top SiO2 interlayer thickness on the retention characteristics of the MIFIS structure. The results of retention characteristics show that the MIFIS structure with thicker top SiO2 has poorer retention characteristics. This is attributed to the de-trapping of interfacial charges trapped at the top SiO2/Hf0.5Zr0.5O2 interface and the depolarization field of the ferroelectric. By inserting a 3.4 nm SiO2 dielectric interlayer between the gate metal TiN and the ferroelectric Hf0.5Zr0.5O2, we achieve a MW of 6.3 V and retention over 10 years. Our work is helpful in the device design of FeFET.

We study the impact of top SiO2 interlayer thickness on the memory window (MW) of Si channel ferroelectric field-effect transistor (FeFET) with TiN/SiO2/Hf0.5Zr0.5O2/SiOx/Si (MIFIS) gate structure. We find that the MW increases with the increasing thickness of the top SiO2 interlayer, and such an increase exhibits a two-stage linear dependence. The physical origin is the presence of the different interfacial charges trapped at the top SiO2/Hf0.5Zr0.5O2 interface. Moreover, we investigate the dependence of endurance characteristics on initial MW. We find that the endurance characteristic degrades with increasing the initial MW. By inserting a 3.4 nm SiO2 dielectric interlayer between the gate metal TiN and the ferroelectric Hf0.5Zr0.5O2, we achieve a MW of 6.3 V and retention over 10 years. Our work is helpful in the device design of FeFET.

In this work, we demonstrate the enlargement of the memory window of Si channel FeFET with ferroelectric Hf0.5Zr0.5O2 by gate-side dielectric interlayer engineering. By inserting a 3 nm Al2 O3 dielectric interlayer between TiN gate metal and ferroelectric Hf0.5Zr0.5O2, we achieve a memory window of 4.1 V with endurance of ~104 cycles and retention over 10 years. The physical origin of memory window enlargement is clarified to be charge trapping at the Al2O3/Hf0.5Zr0.5O2 interface, which has an opposite charge polarity to the trapped charges at the Hf0.5Zr0.5O2/SiOx interface.

We conducted a comprehensive investigation on the influence of TiN thickness and stress on the ferroelectric properties of Hf0.5Zr0.5O2 thin films. TiN top electrode layers with varying thicknesses of 2, 5, 10, 30, 50, 75, and 100 nm were deposited and analyzed. It was observed that the in-plane tensile stress in TiN films increased with the thickness of the TiN top electrode. This is expected to elevate the tensile stress in the Hf0.5Zr0.5O2 film, consequently leading to an enhancement in ferroelectric polarization. However, the effect of stress on the ferroelectric behavior of Hf0.5Zr0.5O2 films exhibited distinct stages: improvement, saturation, and degradation. Our study presents novel findings revealing a saturation and degradation phenomenon of in-plane tensile stress on the ferroelectric properties of polycrystalline Hf0.5Zr0.5O2 films, thereby partially resolving the discrepancies between experimental observations and theoretical predictions. The observed phase transformation induced by tensile stress in Hf0.5Zr0.5O2 films played a crucial role in these effects. Furthermore, we found that the impact of the TiN top electrode thickness on other factors influencing ferroelectricity, such as grain size and oxygen vacancies, was negligible. These comprehensive results offer valuable insights into the influence of stress and TiN top electrode thickness on the ferroelectric behavior of Hf0.5Zr0.5O2 films.