Ronald C. De Vries’s research while affiliated with University of New Mexico and other places

The author presents an overview of a methodology for the automated generation of fault trees for electrical/electronic circuits from a representation of a schematic diagram. Existing computer programs for the generation of fault trees are briefly discussed, and their deficiencies are indicated. The approach presented here is quantitative and uses backtracking. It is illustrated by an example. A prototype computer program has been written to implement the methodology for DC circuits

Consideration is given to the implementation of distributed discrete-event simulation (DDES) using what has been commonly called the Misra approach, after one of its inventors. A major problem with DDES is that deadlock can occur. Therefore, DDES algorithms must either avoid deadlock in the first place, or detect the existence of deadlock when it does occur and eliminate it. J. Misra (1986) proposes the use of null messages as one way to circumvent the deadlock problem. However the number of null messages can become quite large. Methods are presented for reducing the number of null messages through the prediction of channel times. A framework is presented on the basis of which distributed discrete-event simulation can be built for applications that can be decomposed into feedforward and feedback networks

The authors present the design of self-checking sequential machines using standard memory elements, i.e. D , T , or JK flip-flops. The design approach involves cascading the three parts of a sequential machine, i.e. excitation, memory elements, and the output circuit. Parity is used to detect and transmit errors from one part to the next. The conditions for testing D , T , and JK flip-flops and for transmitting errors from their inputs to their outputs are presented; these are shown to exist in normal operation when the design procedure is used. SR flip-flops are found not to have the properties necessary for designing self-checking sequential machines

The relevant definitions are given and a model of self-checking iterative network is presented. A general combinational circuit was developed that is totally self-checking and can detect an error on the input code lines and transmit the error to the output code lines. Thus, an error generated in a cell is transmitted from cell to cell until the last cell is reached. The error, and fault that generated it, can be detected by the checker at the last cell, which can also be made self-checking. The added redundancy increases the amount of logic required to realize the circuit, and the increase depends on the circuit being realized. If z is the number of output code lines for a general cell, a rough estimate of the percent increase in circuitry is 1/z×100