Roland Leißa's research while affiliated with Universität Mannheim and other places

... The literature on accelerating the Smith-Waterman and Needleman-Wunsch algorithms for sequence alignment is extensive [37][38][39][40]. The classical sequence alignment problem without additional heuristics computes the entire dynamic programming matrix for alignment. ...

... In addition, dataflow circuits are necessary for efficient C-to-circuit translation of any software program, as they are capable of handling variable latencies and erratic memory dependencies. Many HLS compilers have included dataflow modeling to generate an FPGA design in which all tasks are pipelined and executed concurrently [34,35]. ...

... In previous work we developed tinyMD [11], a proxy-app (also based on miniMD) created to evaluate the portability of MD applications with the AnyDSL framework. TinyMD uses higher-order functions to abstract device iteration loops, data layouts and communication strategies, providing a domainspecific library to implement pair-wise interaction kernels that execute efficiently on multi-CPU and multi-GPU targets. ...

... In this article, a new development tool, the HLS development platform, is used in combination. To address problems in traditional FPGA development processes, such as long development cycles and tedious debugging processes, this tool uses the C/C++ high-level programming language to design and implement algorithms, and synthesizes the designed program into Verilog language to complete the transformation to the RTL level [19]. In the synthesis process, optimization instructions such as pipeline and loop parallelism can be added to reduce system delay. ...

... Implementing DSLs this way typically promotes a more functional style of programming which allows for abstraction from concerns such as hardware dependence by separating these issue into dedicated functions that are passed to the core algorithms as high-order arguments. While functional programming is often associated with slower execution, AnyDSL has demonstrated that the potential overhead of functional programming is succinctly eliminated using partial evaluation [20,24]. ...

... Recently, domain-extensible compilers such as Delite [14], L [15,16], or AnyDSL [17] provide an extensible set of program abstractions and optimisations, showing potential to mitigate Challenge 1 (Section 2.2). However, domain-extensible compilers remain relatively immature and lack adoption compared to established domain-speci c compilers. ...

... We stress that runtime schedules are entirely independent of the execution state: for any execution state of any P-LLVM program any sequence of basic blocks of that program is a valid runtime schedule. We emphasize this aspect of P-LLVM because it breaks with a standard staple in data-parallel languages: it is common for language semantics to derive scheduling decisions from the execution state, e.g. by deĄning a stack-based scheduling mechanism that takes the threadsŠ branching decisions into account [Farrell and Kieronska, 1996;Leißa, 2017;Habermaier and Knapp, 2012;Karrenberg, 2015;Coutinho et al., 2011;Sampaio et al., 2013;Alur et al., 2017]. We discuss restrictions on the schedule space in Chapter 5. ...

... The goal of CoreGen is three fold. First, CoreGen seeks to provide a rapid high level verification flow that is competitive in performance to traditional optimizing compilers [33] [30] [29]. As a result, the performance of the CoreGen verification flow is a first order design and implementation constraint. ...

... In regular programming languages with vector types where control-ow statements are not overloaded, the code has to be linearized: Non-scalar control ow must be replaced with data ow. The library RaTrace [Pér+17] performs this transformation manually, and uses type inference to avoid writing complex vector types. However, this forces the programmer to mask out inactive lanes by hand in conditionals, and clutters APIs and functions signatures with execution masks. ...

... Other applications rely on domain-specific languages to generate parallel particle methods [21], but this approach requires the development of specific compilation tools that are able to generate efficient code. In this paper we explore the benefits from using the AnyDSL framework, where we shallow-embed [22,23] our domain-specific library into its front-end Impala and can then abstract device, memory layout and communication pattern through higher-order functions. Thus, we use the compiler tool-chain provided by AnyDSL and do not need to develop specific compilation tools for MD or particle methods. ...