Robert Franceschini’s research while affiliated with University of Central Florida and other places

We present an FPGA -based parallel hardware -software architecture for the computation of the Discrete Wavelet Transform (DWT), using the Recursive Merge Filtering (RMF) algorithm. T he DWT is built in a bottom-up fashion in logN steps, successively building complete DWTs by "merging" two smaller DWTs and applying the wavelet filter to only the "smooth" or DC coefficient from the smaller DWTs. The main bottleneck of this algorithm is the data routing process, which can be reduced by separating the computations into two types to introduce parallelism. This is achieved by using a virtual mapping structure to map the input. The data routing bottleneck has been transformed into simple arithmetic computations on the mapping structure. Due to the use of the FPGA -RAM for the mapping structure, the total number of data accesses to the main memory are reduced. This architecture shows how data routin g in this problem can be transformed into a series of index computations

We use a fully timing-driven experimental flow [4] [15] in which a set of benchmark circuits are synthesized into different cluster-based [2] [3] [15] logic block architectures, which contain groups of LUTs and flip-flops. We look across all architectures ...

As reconfigurable devices move to the forefront of mainstream processing, the spectrum of application areas for such devices is also increasing. One such area is image processing. In this paper we present a novel hardware-software codesign architecture for the computation of the Discrete Wavelet Transform (DWT), based on a new Recursive Merge Filtering (RMF) algorithm. The architecture aims at reducing the overall data routing during the computation of the DWT. The method shows how data routing can be transformed into a series of index computations carried out on the reconfigurable device. The architecture applies hardware/software codesign principles for task division among the available processing resources and uses memory resources closer to the FPGA to avoid the main memory accesses and this reduces the processing time and access time. The paper also proposes ideas based on memory bank to further enhance the performance of the proposed architecture. The architecture is based on a dynamically reconfigurable device, the Xilinx XC6200 on the H.O.T Works Board used to carry out the data routing by a series of index computations. The complex computations are restricted to the main processor and the simple addition/subtraction tasks for data routing are based on the FPGA.

This section provides brief background information on distributed simulation, computer generated forces, and ModSAF, which set the context for the research described in this paper. 1.1. Distributed simulation Distributed simulation is an approach to building large-scale simulation models from a set of independent simulator nodes communicating via a network. The simulator nodes each independently simulate the activities of one or more entities in the simulated world and report the attributes (e.g., location and velocity) and actions (e.g., weapons firing) of those entities via the network to the other simulator nodes using a pre-defined communications protocol. In a typical distributed simulation, the simulated entities coexist in a common simulated environment and can interact with each other; their interactions are realized via the exchange of messages in the protocol. One example of a military distributed simulation is the U.S. Army's Close Combat Tactical Trainer (CCTT). In CCTT, which is a real-time system, the simulator nodes typically represent single vehicles, such as tanks or aircraft. CCTT simulators are substantial devices consisting of a simulation computer, a computer image generator, and a physical simulation of the interior of the vehicle being simulated. The human crew of the simulator maneuver their simulated vehicle in the simulated world and interact with (e.g., fire their weapons at) other vehicles.

Abstract only given. Presents an algorithm for text compression that exploits the properties of the words in a dictionary to produce an encryption of given text. The basic idea is to define a unique encryption or signature of each word in the dictionary by replacing certain characters in the words by a special character “*” and retain a few characters so that the word is still retrievable. The question is whether we can develop a better signature of the text before compression so that the compressed signature uses less storage than the original compressed text. This indeed is possible as our experimental results confirm. For any cryptic text the most frequently used character is “*” and the standard compression algorithms can effectively exploit this redundancy in an effective way. Our algorithm produces the best lossless compression rate reported to date in the literature. One basic assumption of our algorithm is that the system has access to a dictionary of words used in all the texts along with a corresponding “cryptic” dictionary. The cost of this dictionary is amortized over the compression savings for all the text files handled by the organization. If two organizations wish to exchange information using our compression algorithm, they must share a common dictionary. We used ten text files from the English text domain to test our algorithm