Ramandeep Kaur's scientific contributions

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Publication (1)

Fig. 1: A conventional single-port SRAM cell
Fig. 4: Proposed Design Block Diagram
Fig. 5: A single cycle waveform of proposed 2R-1W memory with pipelined...
A 6T SRAM cell based pipelined 2R/1W memory design using 28nm UTBB-FDSOI
Conference Paper
Full-text available
  • Sep 2015
Multi-port Static Random Access Memories (SRAM) are essential for shared data structures, especially in distributed, multi-core and multi-processing computing systems. This paper introduces an elementary multi-port memory design which can perform either dual-read or a single-write operation (2R/1W) by efficiently combining the 6 Transistor (6T) sin...
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Citations

... Several techniques were proposed in the literature to overcome disadvantages of power and area consumptions of conventional 1R-1W DP-SRAM. Time Division Multiplexing (TDM) [8], [9] and Replica based [10] designs are among those creating extra read and write ports [11]. TDM based memory read and write operations are sequential with respect to the internal clock of the memory although it seems like a parallel execution with respect to the SoC clock, as the internal memory clock is twice the highest clock of the accessing device in the SoC. ...
Reference: Asynchronous 1R-1W dual-port SRAM by using single-port SRAM in 28nm UTBB-FDSOI technology
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