Rakesh Malik's research while affiliated with Greater Noida Institute of Technology and other places
What is this page?
This page lists the scientific contributions of an author, who either does not have a ResearchGate profile, or has not yet added these contributions to their profile.
It was automatically created by ResearchGate to create a record of this author's body of work. We create such pages to advance our goal of creating and maintaining the most comprehensive scientific repository possible. In doing so, we process publicly available (personal) data relating to the author as a member of the scientific community.
If you're a ResearchGate member, you can follow this page to keep up with this author's work.
If you are this author, and you don't want us to display this page anymore, please let us know.
It was automatically created by ResearchGate to create a record of this author's body of work. We create such pages to advance our goal of creating and maintaining the most comprehensive scientific repository possible. In doing so, we process publicly available (personal) data relating to the author as a member of the scientific community.
If you're a ResearchGate member, you can follow this page to keep up with this author's work.
If you are this author, and you don't want us to display this page anymore, please let us know.
Publications (41)
This paper presents design and harmonic distortion analysis using Volterra series for a 12 V to 1.2 V buck converter designed in the 180 nm BCD8 technology of STMicroelectronics. The series determines the closed-form equations for fundamental, second and third harmonics. From the analysis, the results are 96 %, 97 % and 90 % matched with the simula...
An efficient approach for modeling of time interval error (TIE) due to noise in power delivery networks (PDNs), for current-mode (CM) driver circuits, is presented. Semianalytical expressions relating the PDN noise and TIE are developed based on midpoint delays of the rising and falling edges of the differential signal. The validating examples with...
An efficient methodology for estimation of power supply induced jitter (PSIJ) in high-speed designs is presented. Semianalytical expressions for jitter are derived based on separating the large signal response and the small signal noise response and subsequently combining the results. Proposed simplified relations enable the designers to estimate t...
A 0.065-mm
<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>
single-channel calibration-free 12-b analog-to-digital converter (ADC) sampling at 600 MS/s in 28-nm ultrathin body bias fully depleted silicon on insulator (FD-SOI) is presented. The selected hybrid architecture, incorporating pipeline...
Estimation of jitter in early design cycle of an SoC
is necessary to avoid jitter budget conflicts in the design. In this
paper, an analysis of power supply induced jitter in a commonly
used voltage mode driver architecture in serial links is discussed.
The circuit used for the analysis was designed in 28nm FDSOI
technology but the analysis is tech...
An analysis of power supply induced jitter in a
high speed serial link is presented in this paper. An equivalent
reduced model for serial link is used for the analysis. Jitter
induced by the ripples in power delivery network is analyzed
by a small signal equivalent model. The effect is modeled by a
transfer function which is not technology specific...
Due to advancement in technology and higher demand of frequency, the effect of jitter components, especially inter-symbol interference (ISI), plays significant impact on performance of high speed serial links. The analysis of jitter components is useful for testing of high speed circuits. In this paper, an efficient methodology for estimation of in...
This work holds the objective of investigating the performance of conventional Full Adders (FA) at 28nm regime and then proposes a Transmission Gate (TG) based improved FA circuit of reduced Power Delay Product (PDP). In this design the XOR/XNOR nodes have been optimized to operate at submicron level with lower delay. The work provides full voltage...
This paper proposes methodology for generic system modelling of high speed parallel interfaces. The paper also covers case study of Clock jitter failure analysis in Double data rate Physical layer (DDR2/3) in SOC environment. This Methodology involves breaking down the system in multiple components and generating models for each component to observ...
With the advancement of VLSI technology, the effect of jitter is becoming more critical on high speed signals. To negate the effect of jitter on these signals, the causes of jitter in a circuit need to be identified by decomposing the jitter. In this paper, a comparative analysis of various jitter estimation techniques is presented. The statistical...
![Fig.1.6 Frequency versus phase noise plot [13].](profile/Vijender-Kumar-Sharma/publication/274641024/figure/fig1/AS:613921392189466@1523381674626/Frequency-versus-phase-noise-plot-13_Q320.jpg)
![Fig.1.15 Example of ISI due to bandwidth limitations [19].](profile/Vijender-Kumar-Sharma/publication/274641024/figure/fig8/AS:613921392185361@1523381674968/Example-of-ISI-due-to-bandwidth-limitations-19_Q320.jpg)
![Fig.1.18 Histogram analysis [21].](profile/Vijender-Kumar-Sharma/publication/274641024/figure/fig11/AS:613921396367361@1523381675043/Histogram-analysis-21_Q320.jpg)
Maintaining quality of signal transmission is a major challenge with the increasing speed of data transmission in Nano-scale VLSI technology. The decreasing voltage margins at the same time, makes it even stringent to maintain Power Integrity (PI) and Signal Integrity (SI) in high speed systems. Jitter is an important phenomenon of signal integrity...
This paper presents application of nature inspired algorithms for solving an industrial problem of power delivery network design. To achieve the target impedance in a power delivery network, optimum number of decoupling capacitors and their optimum locations on board are found from thousands of available capacitors. S-parameters based data is used...
Power Integrity is maintained in a high speed system by designing an efficient decoupling network. This paper provides a generic formulation for decoupling capacitor selection and placement problem which is solved by mixed-integer programming. A real-world example is presented for the same. The minimum number of capacitors that could achieve the ta...
This paper presents a top-down design methodology for the design of EBG structures meeting design targets identified in terms of S/Z parameters. The design of EBG structures are based on multiple design considerations of central cell structures as well as cell to cell interconnect structures. Possible iterations of cell structures and cell to cell...
A novel uniplanar electromagnetic band-gap structure to maintain power integrity by suppressing simultaneous switching noise is presented. The proposed EBG structure is having stop-band from 600 MHz to 5.3 GHz and can be used as power plane in high speed systems for minimizing the power noise. Suppression of resonant cavity modes of power plane by...
The Power Integrity problem for high speed systems is discussed in context of selection and placement of decoupling capacitors. Power Integrity is maintained by damping the cavity mode peaks at resonant frequencies using decoupling capacitors. This article focuses on damping cavity mode effects in power delivery networks by the particle swarm optim...
Random jitter (RJ) estimation based on Tail Fit algorithm are generally inaccurate in presence of deterministic components like the presence of sinusoidal jitter (SJ) and duty cycle distortion (DCD). Addition of deterministic jitter changes the standard deviation of the tail region of resulting jitter probability density function. A new methodology...
A novel uniplanar electromagnetic band-gap structure to maintain power integrity by suppressing simultaneous switching noise (SSN) is presented. The EBG structure with stopband from 750 MHz to 5.10 GHz is designed, fabricated and validated using network analyzer. Simulation results are verified by measurements and compared with the earlier publishe...
Power Integrity problem for a high speed power plane is discussed in context of selection and placement of decoupling capacitors. The s-parameters data of power plane geometry and capacitors are used for the accurate analysis including bulk capacitors and VRM, for a real world problem. The optimal capacitors and their optimum locations on the board...
This paper deals with the application of a meta-heuristic optimization algorithm, namely the Cuckoo Search Algorithm in design of the electromagnetic band gap (EBG) structures. These EBG structures are employed for the purpose of suppressing power/ground noise in printed circuit boards. A design example of 2D planar EBG structure in the specified f...
In this paper, a meta-heuristic optimization algorithm is proposed for the design of Electromagnetic Band Gap (EBG) structures to suppress simultaneous switching noise (SSN) on printed circuit boards. This algorithm offers optimized dimensions of EBG unit cell at desired frequency band. A design example of 2D planar EBG structure in the specified f...
System-level signal integrity (SI) and power integrity (PI) problems are taken into account. System-level simulation of high-speed systems with effect of external environment is described. SI and PI issues with complete analysis of package, board, termination, squid card, and decoupling network are shown. Common problems of simulations-passivity vi...
Swarm intelligence is applied to a module of high speed system design problem. To maintain power integrity in a high speed system, an effective methodology for suppressing the cavity-mode anti-resonances' peaks is presented. The optimal values and the optimal positions of the decoupling capacitors are found using three different swarm intelligence...
To maintain Power Integrity in a high speed system, an effective methodology for suppressing the cavity-mode anti-resonances peaks is presented. The optimum values and the optimal positions of the decoupling capacitors are found using Particle Swarm Optimization, which leads to optimum impedance of power plane loaded with decoupling capacitors. Opt...
System level signal integrity and power integrity problems for high speed serial links have been explored in this paper. An example of the USB 2.0 IP has been used in this paper, but the analysis is generic for all serial links. This paper considers signal and power integrity as effects simultaneously. A model is developed to optimize the performan...
Signal Integrity (SI) and Power Integrity (PI) are the most important characteristics for system level design, simulation and analysis of high speed systems. In this paper, HSLINK system is optimized for better SI and PI. Linear models for eye amplitude and jitter are derived by Design of Experiments (DOE). Cost effective solution strategy is also...
Signal Integrity (SI) and Power Integrity (PI) are the most critical issues as the semiconductor industry is moving towards higher operational speeds. Signal Integrity and Power Integrity issues, also referred as electrical integrity issues should be looked at system level rather than treating them as active and
passive networks separately. In thi...
Signal integrity (SI) and power integrity (PI) are the most critical issues for high speed serial links. In this paper, a system perspective of high speed links is discussed with SI and PI analysis. The paper discusses the key parameters affecting the signal and power delivery network for the whole system and also demonstrates the usefulness of con...
Signal Integrity (SI) and Power Integrity (PI) are the most critical issues for higher operational speeds in semiconductor industry. This work identifies and optimizes the parameters of board, package and termination environment, influencing the signal integrity and power integrity of serial link. System level model has been created for USB HSLINK...
Integrated System Level Simulations of high speed serial links are necessary for the channel reliability and robustness. Increasing data rates and sharp transition time require high bandwidth systems. System level simulation are required to optimize channel design keeping cost of implementation at moderate or low level while meeting system level ch...
This paper presents RLC equivalent model of power plane for power distribution network (PDN) in high speed VLSI system consisting of package, board, and voltage regulator module. The frequency independent RLC equivalent model can be easily integrated in any SPICE compatible circuit simulator. SPICE simulation results of the proposed RLC models for...
This paper describes an 11 b ADC realized using a 2.5 b pipelined stage followed by 9 b time interleaved SAR. Presented ADC designed in 65 nm CMOS process occupies 0.3 mm<sup>2</sup> area, achieves 59.1 dB SINAD at 100 Ms/s sampling frequency while dissipating 15 mW power from 1.2 V supply and resulting FOM is 0.20 pJ/step.
This paper describes a novel low power 10-bit 125 Msps pipelined ADC implemented in 65 nm standard digital CMOS process. Proposed ADC implements 2.5 b/stage with amplifier shared between consecutive stages, achieves best in class FOM of 0.27 pJ/step with conversion power of 0.16 mW/Msps. The ADC amplifier employs novel techniques of adaptive biasin...
Citations
... Sys-temVue acts as an intermediate stage between simulation world, as in Matlab; and the real implementation world, as in field programmable gate array (FPGA). It can handle a hardware in the loop (HIL), to get the simulation out into the manufacturing world [3]. SHU et al. present a novel implementation of real-time radar environment simulator with four channels for missile-borne SAR using wideband DRFM technique and parallel computing technique based on FPGA is presented. ...
... Previously, the harmonic analysis of DC-DC buck converter had been discussed in [10]- [12]. In this paper, nonlinear modeling and distortion analysis of complete PDN (from VRM to the load through board and package) has been discussed. ...
![[object Object]](https://i1.rgstatic.net/ii/profile.image/1166762578067456-1655189284300_Q64/Vijender-Kumar-Sharma.jpg)
![[object Object]](https://i1.rgstatic.net/ii/profile.image/1032367191908354-1623146927798_Q64/Jai-Tripathi-2.jpg)
... Using expressions (31), (32), (33) and (34), the distortion quantities for the buck converter because of PSN and input perturbations are written as: ...
... Recently, a few computational efficient analytical approaches have been proposed for predicting the jitter induced by P/G noise. A semi-analytical method for determining jitter of a driver was derived based on the linear equivalent circuit [1]. In [2], an IBIS-based approach was presented where the driver's current-voltage (I-V) curves were further linearized in order to derive the analytical transfer function of the jitter distortion based on the solution of the second-order linear differential equations [2]. ...
![[object Object]](https://i1.rgstatic.net/ii/profile.image/773706167115777-1561477333119_Q64/Ramachandra-Achar.jpg)
... En el presente trabajo se emplea una metodología similar a la planteada por Shah [15] (Figura 1), pues es utilizado ampliamente en la literatura descrita. A excepción de la primera etapa de la metodología, correspondiente al diseño en punto fijo del modelo, el resto de las etapas pueden ser acometidas dentro del flujo de trabajo del HDL Workflow Advisor. ...
![[object Object]](https://i1.rgstatic.net/ii/profile.image/917504343961607-1595761490961_Q64/Alexander-Fell.jpg)
... In [5], a detailed review of power supply induced jitter (PSIJ) in high-speed VLSI circuits is presented. In the article [13], a semianalytical technique is presented to estimate jitter by obtaining the large and small-signal noise responses separately and then combining the results. It uses only a single-bit simulation to estimate jitter. ...
... Various techniques have been proposed to optimize the number of decoupling capacitors in PDNs. Simulated annealing is used in [12] and [13] to minimize the number of decoupling capacitors while satisfying a target impedance. A noise-driven simulated annealing optimization approach is used in [14] to minimize the number of decoupling capacitors in packages for power integrity. ...
... The SNN is only active when the input signals change substantially, leading to very low dynamic power. The leakage power is limited by the nanoscale transistors in the implemented process and can be further improved with advanced techniques or process [34]. ...
![[object Object]](https://i1.rgstatic.net/ii/profile.image/1153052698509313-1651920594926_Q64/Ashish-Kumar-506.jpg)
... Outre le PA, les émetteurs contiennent : des mélangeurs [77], des modulateurs, des oscillateurs (VCO), des convertisseurs [78], des générateurs… Le Tableau 1-2 offre un aperçu des performances des émetteurs dans la bande V. ...
... For high-speed communication links, one of the most important challenges is jitter. The most significant source of timing jitter is power supply induced jitter (PSIJ) [1], [2], [3], [4], [5] and jitter-aware target impedance for power distribution network [6], [7], [8], [9], [10]. The conventional approach to analyze and simulate multiple high-speed interface circuits at the same time in highly integrated systemon-chip system and high pin count system will take a lot of resources and may have non-convergence issue in circuit simulator with power delivery network (PDN) S-parameter model. ...
![[object Object]](https://i1.rgstatic.net/ii/profile.image/286927375880193-1445420225607_Q64/Hiten-Advani.jpg)
