R. Hagelauer’s research while affiliated with Johannes Kepler University of Linz and other places

After a decade of research in the field of wireless sensor networks the energy consumption remains the dominating constraint. Complex algorithms with non-negligible runtimes must be processed by resource-limited nodes, and therefore require in-depth knowledge of the temporal behavior of the software and hardware components. However, state-of-the-art simulators provide either accuracy or scalability and therefore somehow limit the development of such networks. We present a novel and unique methodology for energy-aware, time-accurate, and scalable simulation of wireless sensor networks that considers software, hardware, and network components. Algorithms implemented in C are annotated with binary runtime information and are executed natively on the host cpu, i.e., the cpu where the simulation is run. Arbitrary hardware can be modeled at various levels of abstraction and is simulated together with the software. Important effects such as interrupt processing are simulated accurately. As a proof of concept we implemented the proposed methodology and present STEAM-Sim, a novel simulation environment. We evaluated STEAM-Sim by means of a proprietary networking scenario typically used in industrial wireless sensor networks. Preliminary results regarding scalability and accuracy are presented.

An adaptive DCO (Digital Controlled Oscillator) gain tracking algorithm for an ADPLL (All Digital Phase Locked Loops), which is working as a frequency synthesizer, is presented in this paper. By using this DCO gain real-time tracking method, the requirement of DCO linearity and the complexity of the circuits can be highly decreased. The result shows that with introducing a small amount of training signal the actual DCO gain can be accurately estimated in short time with a fine resolution and the EVM (Error Vector Magnitude) performance is improved significantly. Index Terms ?? DCO Gain Estimation, All Digital Phase Locked Loops, Adaptive Tracking

Since wireless sensor networks (WSNs) are used increasingly in industrial applications, new tight constraints on the timing and power consumption behaviour arise. These constraints cannot be investigated properly by using state-of-the-art simulation tools. In our work we consider and model the WSN at different levels of abstraction in the domains hardware, software, and network. Additionally, the behaviour of the software component executed on a node, which has a major impact on its timing and power consumption, is included in the simulation while maintaining acceptable performance. We show the usefulness and accuracy of our developed methodology using a simple but expressive TDMA-based networking scenario.

In this paper, we present the design of RF filters for a WLAN front-end in a high resistivity silicon copper technology for high performance monolithic active and passive devices. A MATLAB based integrated environment is used to simulate and optimize the wanted inductors. Then the whole designed filter will be simulated in HFSS for final checking. For the first run, the fabricated harmonics filter achieved an insertion loss of less than 0.3dB and 2nd and 3rd harmonic attenuations of more than 30dB and the fabricated band-pass filter (BPF) achieved an insertion loss of less than 2dB and an out of band attenuation of more than 25dB for the WLAN 2.4GHz frequency band. The fabricated harmonics filter and BPF features a size of 0.75×0.67mm2 and 1.0×1.3mm2 respectively.

In this paper, we present a methodology to establish an accurate and power-aware simulation of wireless sensor networks. As the design of software applications running on resource-constrained sensor nodes mainly influences both timing and power consumption in the network, it is crucial to include these components in the simulation. Besides considering the software aspect in the network, it is also important to obtain a detailed and accurate power consumption profile of every hardware module present in the network. Our methodology extends the PAWiS framework, which builds upon the well known discrete event network simulator OMNeT++. The framework was extended to include natively executing real-life application code written in the C language. Using a time-annotation process brings the timing aspect of application code execution into the simulation, and therefore increases simulation accuracy. Moreover, the presented partitioning of the application code into software layers provides easy porting of the simulated code to real sensor nodes. This concept does not impose any restrictions with respect to the target platform used or the OS running on it. To demonstrate the functionality of this approach, the methodology was applied to a real-world networking test scenario, and the achieved simulation results were compared to real-world measurements. The performance of the simulation environment was evaluated and is presented.

The trend for low-cost, small dimension, thin profile, multi-function and multi-mode handheld wireless devices are required by the future user. In this paper, we present the design of an Electrostatic Discharge (ESD)-protection free band-pass filter (BPF) in an improved high resistivity silicon copper technology for the monolithic integration of active and passive devices. Inter-digital metal capacitors instead of typical Metal-Isolator-Metal (MIM) capacitors are used for better quality factor and higher breakdown voltage of up to 800 V. Electromagnetic (EM) simulation was extensively used in this design for inductor and filter optimization. The fabricated device by the first run has an insertion loss of less than 2 dB and an out of band attenuation of more than 25 dB for the WLAN 2.4 GHz frequency band and features a size of 1.0×1.3 mm2.

We present a methodology and a toolset for power aware HW/SW co-simulation including real-life application code at network level. The toolset consists of the known OMNeT++ network simulation environment and the PAWiS framework, which was extended to include time-annotated and natively executing C code, and allows detailed analysis of the power consumption of single modules in the network. In conjunction with the support of interrupt handling, this especially addresses the needs of applications running on nodes of wireless sensor networks (WSNs). The presented partitioning of the application into platform-dependent and platform-independent SW layers provides easy porting of the simulated code to real sensor nodes. Therefore the established simulation environment supports the development, implementation and verification of energy optimized protocols for real-time industrial applications using WSNs. To demonstrate the functionality of this approach, the methodology was applied to a simple real-world networking test scenario and the achieved simulation results are compared to real-world measurements.

Modern multi-band and multi-mode handheld wireless devices require novel approaches for the integration of passive elements into the radio front-end. In this paper, we present the design of an electrostatic discharge (ESD)-protection-free harmonic filter using an improved high-resistivity silicon copper technology for the monolithic integration of active and passive devices. Typical metal-isolator-metal (MIM) capacitors are replaced by inter-digital metal capacitors which provide a high breakdown voltage of up to 800 V. As the machine-mode ESD voltage is lower than 500 V, this filter can operate without ESD protection. In this design, electromagnetic (EM) simulation was used extensively for inductor and filter optimization. The fabricated device has an insertion loss of less than 0.3 dB and 2^nd and 3^rd harmonic attenuations of more than 30 dB for the WLAN 2.4 GHz frequency band and features a size of 0.75×0.67 mm².

This paper presents a modified Gilbert type mixer which is fabricated in a 200 GHz f_T SiGe:C bipolar technology and well suited for 77 GHz bi-static automotive radar applications. The measured single sideband noise figure (NF_SSB), conversion gain (CG), and input-referred 1 dB compression point (ICP) of this mixer are 10.8 dB, 21.5 dB, and -5 dBm, respectively. The current consumption is 21 mA under 3.3 V power supply. This mixer shows state-of-the-art noise figure, conversion gain traded-off with 1 dB compression point, and low power consumption.

A single-chip, dual-band transceiver for CDMA2000 is presented. The design supporting the North American cellular and PCS bands features a complete zero-IF receiver, a direct-conversion transmitter and two fully integrated synthesizers with VCOs. The analog receiver front-end comprises two self-matched wideband LNAs, a highly linear demodulator and a third-order baseband filter. In a test version I/Q ADCs and a digital front-end (DFE) to provide channel and matched filtering are included to demonstrate the performance of a fully integrated analog/digital line-up. Measured maximum SNR values of 23 dB and 25 dB for PCS and Cell bands, respectively, are achieved. The transmitter comprises baseband buffers and filters, an I/Q-modulator and separate output drivers for each band. An analog gain control (AGC) for realization of a dynamic range is implemented and a maximum output power of at a total CDG4 urban current of 34 mA is achieved for the PCS band. Measured ACPR1 and values are and 0.998 for the Cell band and and 0.995 for the PCS band, respectively. The chip is fabricated in a 0.13 RF-CMOS process, occupies a die size of 8.4 and operates with a 2.5 V supply.