February 1999
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This paper presents a systematic approach to design CMOS chips with concurrent picture acquisition and processing capability. Pixel smartness is achieved by exploiting the Cellular Neural Network paradigm [1], incorporating at each Spixel an analog computing cell which interacts with those of nearby Spixels. We propose a current-mode technique for CNNSpixel chips and give measurements from two 16 16 prototypes in a single-poly double-metal CMOS n-well 1.6m technology. One of these prototypes is designed for the application of Connected Component Detection (CCDet) [2], and the other to calculate the Radon Transform (RT) [3] of an input image. The CCDet chip obtains a density of ~89 Spixels (sensory+regulation+processing) per mm 2 , with a power consumption of 105W per Spixel. The sensory+regulation circuitry amount to ~30% of the total Spixel pixel area and the rest corresponds to the processing circuitry. Area and power figures for the RT chip are similar. These area and power figur...