Pelopidas Tsoumanis's research while affiliated with University of Thessaly and other places

Publications (7)

Article
Full-text available
Due to continuous CMOS technology downscaling, Integrated Circuits (ICs) have become more susceptible to radiation-induced hazards such as soft errors. Thus, to design radiation-hardened and reliable ICs, the Soft Error Rate (SER) estimation constitutes an essential procedure. An accurate SER evaluation is provided based on a SPICE-oriented electri...
Conference Paper
Cosmic radiation resulting in transient faults to the combinational logic of Integrated Circuits (ICs), constitutes a major reliability concern for space applications. In addition, continuous technology shrinking allows for the presence of Single-Event-Multiple-Transients (SEMTs), and renders modern chips more susceptible to soft errors. The study...
Article
Full-text available
Integrated circuit susceptibility to radiation-induced faults remains a major reliability concern. The continuous downscaling of device feature size and the reduction in supply voltage in CMOS technology tend to worsen the problem. Thus, the evaluation of Soft Error Rate (SER) in the presence of multiple transient faults is necessary, since it rema...
Conference Paper
In the VLSI field, reliability of chips is a major issue and it becomes more significant considering the continuous technology down-scaling. Modern chips are extremely sensitive to various factors such as radiation and, thus, it is crucial to implement tools for the evaluation of their vulnerability to the aforementioned hazards. We present a Soft...

Citations

... The most widely used technique is Triple-Modular Redundancy (TMR), where fault tolerance is accomplished by triplicating the original module and inserting a two-out-of-three majority voting [7]. TMR may be utilised either for SEUs, and be applied at the FF level, or for SETs, and be applied to the most sensitive circuit gates [8], which critically affect circuit area and performance. Other possible approaches utilise three separate clock trees, with timing offset between them, or inserting a temporal filter at the TMR circuit structure [9], having significantly lower complexity and area cost. ...
... An integrated tool based on Monte-Carlo simulations, modeling the three masking phenomena (logical, electrical, and timing) that affect the probability that a transient fault will become a soft error and emphasizing on SEMTs analysis, is utilized for the SER evaluation process [26]. An SEMT occurs when a heavy ion strikes a sensitive area over the chip, producing glitches on adjacent cells. ...
... To accurately estimate the SER of a design, it is indispensable to model sufficiently and accurately the three mechanisms that are able to impede an SET from propagating through a circuit and, eventually, being latched by the flip-flops (FFs), thus producing a soft error. These effects are logical, electrical, and timing-masking [3]. The logical masking occurs when an SET is masked on a subsequent gate because one of the other inputs is in a controlling value. ...
... In[18], the authors measure the SER of a processor starting from a technology response model up to application masking.Only the injected errors from lower levels, which were latched by a memory element, are considered in the higher level and, thus, simulation time is reduced due to masking. In[52], a Monte-Carlo-based fault injection technique is proposed, taking into account multiple faults. In order to obtain accurate results, the injected nodes are selected according to their proximity to the error source in the place and route diagram. ...
... An SER estimation approach was presented for evaluating the impacts of METs in combinational circuits as well as and sequential ones that is based on the Boolean Decision Diagrams (BDDs) [4]. In [30], an SER estimation approach was introduced for sequential circuits, which is based on Monte-Carlo simulations which have taken METs into account in its estimation process. Authors in [8] proposed a layout-based soft error rate estimation framework, which have considered METs originated from the device level in its circuit level analysis. ...