P.G. Gulak’s research while affiliated with University of Toronto and other places

A CMOS digital pixel sensor (DPS) VLSI architecture with in-pixel one-bit quantization is presented. A single column-parallel comparator is shared by all pixels in the column. This results in a compact 3-T pixel implementation. By eliminating the in-pixel source follower the pixel effective power dissipation is reduced by over two orders of magnitude compared to a conventional 3-T pixel. A 64×64 DPS test prototype with 10μm pixel pitch has been fabricated in 0.35μm standard CMOS and experimentally characterized.

A multi-color fluorescent contact sensing microsystem is presented. The microsystem employs a CMOS field-modulated color sensor (FCS) to spectrally detect and differentiate among multiple emission bands, requiring only one on-CMOS longpass filter. A FCS prototype has been fabricated in a standard 0.35μm CMOS technology. The multi-color imaging capability of the FCS microsystem has been validated in the detection of green-emitting and red-emitting quantum dots (QDs) with QD concentration detection limits of 313nM and 78nM, respectively.

The high spectral efficiency offered by multiple-input-multiple-output (MIMO) technology has made it the technology-of-choice in many standards like IEEE 802.16e/m (WiMAX) and the long term evolution (LTE) project and emerging 4G systems. One challenge to the widespread adoption of MIMO technology is the design of high-throughput detectors with near maximum-likelihood (ML) performance and cost-effective VLSI realization for a large number of antennas and constellation order.

An integrated bacterial detection chip is implemented in 0.18 mum CMOS technology. The chip has been tested using pyocins as biological detecting elements along with the study of electrical noise generated in an integrated nanowell to detect the presence of two different bacterial clinical isolates of Pseudomonas aeruginosa . The chip successfully identifies the presence of bacterial strains sensitive to the pyocin in less than 10 minutes. The effect of bacterial cell concentration is also presented in the experimental results. The chip consumes 122 muW from 3.3 V supply for two recording channels and occupies an area of 0.48 mm² in a 0.18 mum standard CMOS process.

This paper presents an integrated sensor for identifying bacteria that addresses drawbacks of traditional detection techniques by combining the specificity of phages with the sensitivity of integrated electronic circuits. This is the first silicon-based implementation known to date; it uses standard CMOS technology, does not require noble-metal electrodes and co-integrates active circuitry on the same substrate as the measurement site containing the bacteria. The chip was fabricated in 0.18 mum CMOS technology using thick-oxide transistors and consumes 122 muW with a 3.3 V supply for two recording channels.

In this paper we propose a novel algorithm for PAPR reduction of an OFDM system, based on a companding scheme. In this method a compressing polynomial is appended to the IFFT block at the transmitter and at the receiver the FFT block is combined with a reverse expanding function where the iterative Jacobi's method is used for solving equations. The proposed method entails less complexity at the transmitter in comparison with other PAPR reduction algorithms. It also requires less increase in SNR for the same BER compared to other companding methods. A trade off between complexity and performance can set the order of compressing polynomial and the number of iterations for the proposed algorithm at the receiver

The regular and repetitive nature of the sequential Monte Carlo (SMC) method makes it very attractive for implementation using parallel and pipelined architectures. This paper develops a VLSI architecture for the hardware implementation of the SMC algorithm using bootstrap filter. A flat fading wireless channel is considered as our framework on which the channel estimator is designed and implemented using the SMC method. The design and verification activities at the algorithm level, architecture level, and the circuit level are reviewed. The proposed architecture is verified with an FPGA implementation.

We propose a parallel architecture for implementing the interpolation step in the Koetter-Vardy soft-decision Reed-Solomon decoding algorithm. The key feature is the embedding of both a binary tree and a linear array into a two-dimensional array processor, enabling fast polynomial evaluation operations. An FPGA interpolation processor was implemented and demonstrated at a clock frequency of 23 MHz, corresponding to decoding rates of 10-15 Mbps.

A 0.35μm CMOS analog decoder for a 4-state, rate 1/3, block length 16 turbo code operates at 13.3Mb/s and latency of 1.2μs and consumes 13.9nJ per decoded bit with a 3.3V supply. The 1.42mm² core IC implements two logarithmic domain MAP decoders and a fully programmable analog interleaver that is configured at power-up.

This paper examines Reed-Solomon time-domain and frequency-domain decoder implementations in both software and hardware. The focus was on designing area-efficient, low-power and low-complexity decoders suitable for today's moderate data-rate applications. Two decoder chips were designed using a synthesized standard cell library in a 0.18 μm CMOS process, targeting a 160 Mbps decoding rate. The time-domain decoder was fabricated with a core area of 1.50 mm².