Noriyoshi Yoshida’s research while affiliated with Hiroshima City University and other places

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Publications (36)


A Divide-and-Conquer Approach to the Minimum k -Way Cut Problem
  • Article

February 2002

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154 Reads

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14 Citations

Algorithmica

Yoko Kamidoi

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Shin'ichi Wakabayashi

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Noriyoshi Yoshida

This paper presents algorithms for computing a minimum 3 -way cut and a minimum 4 -way cut of an undirected weighted graph G . Let G=(V, E) be an undirected graph with n vertices, m edges, and positive edge weights. Goldschmidt and Hochbaum presented an algorithm for the minimum k -way cut problem with fixed k , that requires O(n 4 ) and O(n 6 ) maximum flow computations, respectively, to compute a minimum 3 -way cut and a minimum 4 -way cut of G . In this paper we first show some properties on minimum 3 -way cuts and minimum 4 -way cuts, which indicate a recursive structure of the minimum k -way cut problem when k = 3 and 4 . Then, based on those properties, we give divide-and-conquer algorithms for computing a minimum 3 -way cut and a minimum 4 -way cut of G , which require O(n 3 ) and O(n 4 ) maximum flow computations, respectively.


A timing-driven placement algorithm with the Elmore delay model for row-based VLSIs

December 1997

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15 Reads

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2 Citations

Integration

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Shin'ichi Wakabayashi

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Mitsuhiro Ono

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[...]

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Noriyoshi Yoshida

In this paper, we present a timing-driven placement algorithm for standard cell layout, and propose a path-based timing-driven placement algorithm. To estimate the accurate interconnection delay, the proposed algorithm adopts the Elmore delay model [8] so that we can apply the proposed algorithm to wider technologies than the conventional algorithms. The proposed algorithm is based on hierarchical partitioning and nonlinear programming, and consists of three phases. In the first phase, the algorithm produces an initial placement by a timing-driven min-cut partitioning algorithm. Next, an iterative improvement phase improves the initial placement by nonlinear programming. The improvement problem is formulated as the problem of minimizing the total wire length subject to timing constraints. Finally, a row assignment phase considering timing constraint arranges cells in rows. From the experimental results comparing with RITUAL [29], the proposed algorithm is much better than RITUAL in regard to the maximum violation ratio, the total wire length, and the cut size, and is more effective in point of the interconnection delay model and its extendability.


Fig. 1. The floor connection graph G r = (V r ; E r ).
Fig. 2. Outline of phase 1.
Fig. 3. Channel and subchannels.
Fig. 4. Classification of nets in the subchannel sc i. bottom sides of the channel and the net list N of the channel, the problem is to determine a pin assignment so as to minimize the ordered pair (D; T L) with respect to the lexicographical order, where (D 0 ; T L 0 ) < (D; 00 T L 00 ) if and only if D 0 < D 00 , or D 0 = D 00 and T L 0 T L 00 .
Fig. 5. (a) jMLS i [ LS i (T j )j + jLP i j + jIP i j jsc i j. (b) jMLS i [ LS i (B k )j + jLP i j + jIP i j < jsc i j. Pin assignment in a subchannel.

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Pin assignment with global routing for VLSI building block layout
  • Article
  • Full-text available

January 1997

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397 Reads

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6 Citations

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

In this paper, we will consider global routing and pin assignment in VLSI building block layout, and present an efficient algorithm which integrates global routing, pin assignment, block reshaping and positioning. The general flow of the proposed algorithm is the same as the one proposed in by Cong in 1991 [1] and consists of two main phases. The first phase is to determine not only global routes and coarse pin assignment in the same way as [1], but also shapes and positions of blocks. The second phase is to compute the final pin assignment for channels. We generalize the channel pin assignment (CPA) problem in [1], in which the CPA problem is formulated for only channels formed by two blocks, to the CPA problem for channels formed by multiple blocks. We will propose a linear time optimal channel pin assignment algorithm, which is an extension of the algorithm in [1]. Experimental results show the effectiveness of the proposed algorithm

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A three-layer over-the-cell multi-channel router for a new cell model

December 1996

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19 Reads

Integration

This paper proposes a new cell model for over-the-cell routing, and presents a heuristic three-layer over-the-cell multi-channel routing method for the new cell model. In the proposed cell model, terminals can be placed arbitrarily on the second metal (M2) layer of a cell so that each cell does not require the extra routing region on the first metal (M1) layer of a cell to align terminals. Unlike conventional cell models, some parts of the M2 layer may also be utilized for intra-cell routing in order to reduce the chip area. Therefore the size of a cell with the proposed cell model can be smaller than that with conventional cell models.The proposed three-layer over-the-cell routing method consists of three phases. In order to utilize the proposed cell model effectively, in phase 1, we simultaneously handle all channels to determine the most effective routing patterns from the set of possible routing patterns to minimize the chip area. In phase 2, for the routing patterns of nets selected in phase 1, over-the-cell routing nets are selected by a new greedy algorithm considering obstacles in over-the-cell regions. Finally, in phase 3, the conventional three-layer channel routing algorithm is applied for remaining nets. From the experimental results with MCNC benchmarks, the proposed cell model and routing algorithm produce the smaller height of layouts as compared to those produced by conventional cell models and algorithms, and the effectiveness of the proposed cell model and routing method was shown.


Standard cell global routing algorithm with net selection for over-the-cell routing

December 1995

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8 Reads

Electronics and Communications in Japan (Part III Fundamental Electronic Science)

In the detailed routing for VLSI standard cell layout design, the over-the-cell channel routing, which utilizes the over-the-cell region as the routing region, has been proposed. In this design method, after determining the net assignment to each channel in the global routing step, the track assignment both in channel and on over-the-cell regions is performed by an over-the-cell channel router. However, conventional global routing algorithms do not assume over-the-cell channel routing but conventional channel routing. Therefore, the minimization of channel density does not always successfully lead to the minimization of the final channel height. This paper presents a new global routing method for standard cell layouts to determine global routes for each net in both channel and over-the-cell regions simultaneously. the standard cell layout design system GLORIA based on the proposed algorithm is developed, and the experimental results compared with the conventional global routing method that performs the over-the-cell channel routing after global-routing with Timber Wolf-SC4.2c are reported. Experimental results showed that the proposed routing algorithm can route about 18.4 percent fewer number of tracks than the conventional routing method, and the effectiveness of the proposed method is shown. the experimental results of applying the proposed method to the three-layer routing layout model also are presented.


Floorplanning method with topological constraint manipulation in VLSI building block layout

December 1994

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3 Reads

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2 Citations

This paper presents a heuristic floorplanning method that improves the method proposed by Vijayan and Tsay. It is based on tentative insertion of constraints, that intentionally produces redundant constraints to make it possible to search in a wide range of solution space. The proposed method can reduce the total area of blocks with the removal and insertion of constraints on the critical path in both horizontal and vertical constraint graphs. Experimental results for MCNC benchmarks showed that the quality of solutions of the proposed method is better than [7], [8] by about 15% on average, and even for the large number of blocks, the proposed method keeps the high quality of solutions.


Graph bisection algorithm based on subgraph migration

December 1994

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5 Reads

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1 Citation

The graph bisection problem is to partition a given graph into two subgraphs with equal size with minimizing the cutsize. This problem is NP-hard, and hence several heuristic algorithms have been proposed. Among them, the Kernighan-Lin algorithm and the Fiduccia-Mattheyses algorithm are well known, and widely used in practical applications. Since those algorithms are iterative improvement algorithms, in which the current solution is iteratively improved by interchanging a pair of two nodes belonging to different subgraphs, or moving one node from one subgraph to the other, those algorithms tend to fall into a local optimum. In this paper, we present a heuristic algorithm based on subgraph migration to avoid falling into a local optimum. In this algorithm, an initial solution is given, and it is improved by moving a subgraph, which is effective to reduce the cutsize. The algorithm repeats this operation until no further improvement can be achieved. Finally, the balance of the bisection is restored by moving nodes to get a final solution. Experimental results show that the proposed algorithm gets better solutions than the Kernighan-Lin and Fiduccia-Mattheyses algorithms.


Optimal channel pin assignment algorithm for hierarchical building-block layout design

October 1993

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2 Reads

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1 Citation

This paper presents a linear time optimal algorithm to a channel pin assignment problem for hierarchical building-block layout design. The channel pin assignment problem is to determine positions of the pins of nets on the top and the bottom sides of a channel, which are partitioned into several intervals, and the pins are permutable within their associated intervals. The channel pin assignment problem has been shown NP-hard in general. We present a linear time optimal algorithm for an important special case of the problem, in which there is at most one pin of a net within each interval in the channel. The proposed algorithm is optimal in a sense that it can minimize both the channel density and the total wire length of the channel. We also discuss how ti apply our algorithm to the pin assignment in the L-shaped and staircase channels. Experimental results indicate that substantial reduction in both channel density and estimated total wire length can be obtained by permuting pins in each interval. Combining the proposed algorithm with a conventional channel router, results of channel routing also achieve large amount of reduction of the number of tracks, total wire length, and the number of vias.


A parallel algorithm fork-way graph partitioning

March 1993

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2 Reads

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2 Citations

Electronics and Communications in Japan (Part III Fundamental Electronic Science)

With the recent development of semiconductor integration technology, the amount of data that must be handled in the layout design of VLSI is increasing rapidly. Even if the improvement of the processing speed of the computer in the future is considered, it is desired to develop a high-speed layout algorithm compared to the conventional method. This paper discusses the k (> 2)-way graph partitioning problem, which is one of the most basic problems concerning the layout design. A parallel algorithm is proposed. The general method to solve this problem has been to apply hierarchically the two-way graph partitioning algorithm. In this method, the algorithm can easily be executed in parallel by operating a number of processors at each hierarchy. A problem then is the efficiency of the processor and the computation time. This paper considers the k-way graph partitioning and proposes a new method called nonhierarchical k-way graph partitioning, aiming at the education of the computation time by parallel processing. In general, it is considered difficult to improve the speed sufficiently by the parallel processing, while maintaining the same accuracy of the solution as that of the sequential algorithm. In this paper, the effectiveness of the proposed algorithm is shown by a simulation experiment on the sequential computer.


A fast heuristic algorithm for hypergraph bisection

July 1991

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16 Reads

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5 Citations

Proceedings - IEEE International Symposium on Circuits and Systems

Presents an efficient heuristic algorithm for the min-cut bisection of hypergraphs. In this algorithm, first, a given hypergraph is transformed into a graph called the netgraph, and then a solution is found on this netgraph. Since a netgraph can explicitly represent the weight of nodes of a hypergrap, it is easy to partition a hypergraph into two hypergraphs with the same size. The computation time of the proposed method is O ( m 2), where m is the number of nodes of a given hypergraph. Simulation results show that the proposed method produces better solutions in a shorter time compared with existing, methods, and that the solution is always balanced with the size of the partitioned hypergraphs


Citations (13)


... At present there are a number of methods for prevention, avoidance and detectionrepairing of the deadlocks (see [9,32,10)). Very often deadlock detection methods are based on distributed maintenance of the "wait-for-graph", that shows which process is waiting for a resource held by which other process [13,28,5,26,27). Deadlock detection is reduced to finding cycles in this graph. ...

Reference:

OCCAM-Oriented Software Tools
DEADLOCK DETECTION AND RECOVERY IN DISTRIBUTED DATABASE SYSTEMS.
  • Citing Article
  • January 1984

... Fukunaga et al. [16] proposed a large-step Markov Chain (LSMC) algorithm which generates new solutions by making big "jumps" from low-cost local minima. These solutions are then used as starting solutions in FM to generate new local minima (also see Isomoto et al. [26]). Liu et al. [32] proposed a gradient Fiduccia-Mattheyses algorithm (GFM) that alternates FM refinements with gradient descents. ...

Graph bisection algorithm based on subgraph migration
  • Citing Article
  • December 1994

... The p-median problem is to place p facilities so that the total distance from all customers to their corresponding closest facilities is minimized (Colmenar et al. 2018;Jánošíková et al. 2017;Wang et al. 2018). The p-center problem is to place p facilities in the network on such a way that the maximum distance from each customer to its closest facility is minimized (Callaghan et al. 2017;Kikuno et al. 1980;Tüzün Aksu, Ocak 2012). The maximal coverage location problem is to place one or more facilities in the network on such a way that all customers are covered (served) within a predefined radius from at least one facility (Berman et al. 2016;Blanquero et al. 2016;Farahani et al. 2012). ...

NP-completeness of some type of p-center problem
  • Citing Article
  • December 1980

Discrete Applied Mathematics

... A correction in the optimized design is performed by manipulating the constraints that are additionally augmented into the design. Note that methods that facilitate constraint manipulation have already been used for other VLSI optimization tasks [24]. ...

Floorplanning method with topological constraint manipulation in VLSI building block layout
  • Citing Article
  • December 1994

... Though simple to define, such "grouping" problems often pose significant challenges in practical settings because it is not always easy to judge whether the imposed constraints can be satisfied. Indeed many such problems including those concerning graph partitioning (Hertz et al., 2008;Isomoto et al., 1993;Jensen and Toft, 1994;Nakano1 et al., 1995), school and university timetabling (Lewis, 2008;McCollum et al., 2010), sports fixture scheduling (de Werra, 1988;Kendall et al., 2010;Rasmussen and Trick, 2008), load balancing (Falkenauer, 1998), and frequency assignment (Aardel et al., 2002;Valenzuela, 2001), are known to be NP-hard (Garey and Johnson, 1979;Karp, 1972), implying that we cannot hope to establish polynomially bounded algorithms for solving them in the general sense. ...

A parallel algorithm fork-way graph partitioning
  • Citing Article
  • March 1993

Electronics and Communications in Japan (Part III Fundamental Electronic Science)

... In this work, we propose an error-free bundling approach that speeds up the wire length estimation, especially when the interconnection scale is large. Our approach is based on the fact that the total HPWL of the nets spanning between two blocks forms a piecewise linear convex function with respect to the relative position of the two blocks [13, 17]. With this function implemented as a lookup table, we can compute the total wire length promptly and precisely by binary-searching the table instead of scanning the nets one by one. ...

Improvement of one-dimensional module placement in VLSI layout design
  • Citing Article
  • July 1991

Electronics and Communications in Japan (Part III Fundamental Electronic Science)

... However, these algorithms are still exponential in complexity. Meanwhile, linear time algorithms for series-parallel graphs, k-degenerated graphs, and trees are presented in [31], [32], and [33], respectively. ...

A Linear Algorithm for the Domination Number of a Series-Parallel Graph
  • Citing Article
  • March 1983

Discrete Applied Mathematics

... The bisection width of a hypergraph H is the minimum number of edges in a bisection, and we again denote it by bw(H). The study of hypergraph bisection width has attracted attention from the algorithmic point of view [15,25,35]. A particular topic of interest has been the hypergraph-generalisation of the s-t cut problem. ...

A fast heuristic algorithm for hypergraph bisection
  • Citing Conference Paper
  • July 1991

Proceedings - IEEE International Symposium on Circuits and Systems

... Deadlock detection/resolution is an important problem in a distributed system and much attention has been devoted to it in the past few years. Many distributed deadlock detection/resolution algorithms have been proposed, however, most of them either have not given a correctness proof 1, 2, 3] or have given an informal proof by using intuitive operational arguments 4,5,6]. Intuitive operational arguments are prone to errors, and many of the published algorithms have been found to be incorrect 4,5,1,3]. ...

A Distributed Algorithm for Deadlock Detection and Resolution.
  • Citing Conference Paper
  • January 1984

... For a brief review about recent developments in this field, we refer the reader to [60] for the minimum 3-cut problem, [61] for the minimum 3-and 4-cut problem and [62] for the minimum 5-and 6-cut problem. Further deterministic algorithms, based upon the cactus representation or maximum flow computation, can be found in [63][64][65]. In case of an interest in network disintegrations for a given number of links, the approach based on minimum k-cuts is not applicable because in many road networks it would lead to finding only the nodes with one link connecting them to the rest of the network. ...

A Divide-and-Conquer Approach to the Minimum k -Way Cut Problem
  • Citing Article
  • February 2002

Algorithmica