Nestor Evmorfopoulos's research while affiliated with University of Thessaly and other places

Publications (33)

Preprint
Full-text available
The rapid growth of circuit complexity has rendered Model Order Reduction (MOR) a key enabler for the efficient simulation of large circuit models. MOR techniques based on moment-matching are well established due to their simplicity and computational performance in the reduction process. However, moment-matching methods based on the ordinary Krylov...
Article
Full-text available
Due to continuous CMOS technology downscaling, Integrated Circuits (ICs) have become more susceptible to radiation-induced hazards such as soft errors. Thus, to design radiation-hardened and reliable ICs, the Soft Error Rate (SER) estimation constitutes an essential procedure. An accurate SER evaluation is provided based on a SPICE-oriented electri...
Article
Full-text available
As process geometries shrink below 45 nm, accurate and efficient gate-level timing analysis becomes even more challenging. Modern VLSI interconnects are more resistive, signals no longer resemble saturated ramps, and gate input pins exhibit a significant Miller effect. Over recent years, the semiconductor industry has adopted current source models...
Article
Full-text available
The integration of more components into modern integrated circuits (ICs) has led to very large RLC parasitic networks consisting of millions of nodes that have to be simulated in many times or frequencies to verify the proper operation of the chip. Model order reduction (MOR) techniques have been employed routinely to substitute the large-scale p...
Conference Paper
Full-text available
During the past decade, Model Order Reduction (MOR) has become key enabler for the efficient simulation of large circuit models. MOR techniques based on moment-matching are well established due to their simplicity and computational performance in the reduction process. However, moment-matching methods based on the ordinary Krylov subspace are usual...
Preprint
During the past decade, Model Order Reduction (MOR) has become key enabler for the efficient simulation of large circuit models. MOR techniques based on moment-matching are well established due to their simplicity and computational performance in the reduction process. However, moment-matching methods based on the ordinary Krylov subspace are usual...
Article
During the past decade, model order reduction (MOR) has become key enabler for the efficient simulation of large circuit models. MOR techniques based on balanced truncation (BT) offer very good error estimates and can provide compact models with any desired accuracy over the whole range of frequencies (from dc to infinity). However, in most applica...
Conference Paper
Full-text available
The pessimistic nature of conventional static timing analysis has turned the attention of many studies to the exploitation of the dynamic data-dependent excitation of paths. Such studies may have revealed extensive dynamic timing slacks (DTS), however, they rely on frameworks that inherently make worst-case assumptions and still ignore some data-de...
Conference Paper
Cosmic radiation resulting in transient faults to the combinational logic of Integrated Circuits (ICs), constitutes a major reliability concern for space applications. In addition, continuous technology shrinking allows for the presence of Single-Event-Multiple-Transients (SEMTs), and renders modern chips more susceptible to soft errors. The study...
Article
Full-text available
Integrated circuit susceptibility to radiation-induced faults remains a major reliability concern. The continuous downscaling of device feature size and the reduction in supply voltage in CMOS technology tend to worsen the problem. Thus, the evaluation of Soft Error Rate (SER) in the presence of multiple transient faults is necessary, since it rema...
Conference Paper
Full-text available
The verification of integrated Circuits (ICs) in deep submicron technologies requires that all mutual inductive effects are taken into account to properly validate the performance and reliable operation of the chip. However, the inclusion of all mutual inductive couplings results in a fully dense inductance matrix that renders the circuit simulatio...
Conference Paper
Full-text available
Signoff timing analysis is essential in order to verify the proper operation of VLSI circuits. As process technologies scale down towards nanometer regime, the fast and accurate timing analysis of interconnects has become crucial, since interconnect delay represents an increasingly dominant portion of the overall circuit delay. It is a common view...
Conference Paper
The integration of more components into modern Systems-on-Chip (SoCs) has led to very large RLC parasitic networks consisting of million of nodes, which have to be simulated in many times or frequencies to verify the proper operation of the chip. Model Order Reduction techniques have been employed routinely to substitute the large scale parasitic m...
Article
Efficient full-chip thermal simulation is among the most challenging problems facing the EDA industry today, due to the need for solution of very large systems of equations that require unreasonably long computational times. However, in most cases, temperature is not required to be computed at every point of the IC but only at certain hotspots, in...
Conference Paper
The integration of more components into ICs due to the ever increasing technology scaling has led to very large parasitic networks consisting of million of nodes, which have to be simulated in many times or frequencies to verify the proper operation of the chip. Model Order Reduction techniques have been employed routinely to substitute the large s...
Article
Full-text available
Efficient full-chip thermal simulation is among the most challenging problems facing the EDA industry today, especially for modern 3D integrated circuits, due to the huge linear systems resulting from thermal modeling approaches that require unreasonably long computational times. While the formulation problem, by applying a thermal equivalent circu...
Conference Paper
Full-text available
The complexity of modern very large scale inte grated circuits renders circuit simulation very essential in the design process, as it is the only feasible way to verify circuit's behaviour prior to manufacturing. The heart of circuit simulation relies on the solution of huge systems resulting after the modelling using Modified Nodal Analysis. Matri...
Conference Paper
Full-text available
Manufacturing process variation in sub-20nm processes has introduced ever increasing overhead in Static Timing Analysis (STA) in order to guarantee the reliable operation of the circuit. Chip designers apply corner-based analysis and add guard-bands to design parameters in order to take into account the impact of process variation on timing. Howeve...
Article
Efficient analysis of on-chip power delivery networks is one of the most challenging problems facing the electronic design automation industry today. The fast dc and transient simulation of power grids is necessary to determine the proper operation of the integrated circuits at the design phase, but is made very difficult by the sheer size of moder...

Citations

... Paper [7] deals with the effect of time and amplitude variations on the soft error rate (SER) in VLSI circuits. An accurate SER evaluation is provided based on a SPICE-oriented electrical masking analysis combined with a TCAD characterization process. ...
Reference: MOCAST 2021
... Prior works regarding the solution of Korhonen's equation can be classified into two types of approaches. Analytical approaches [4] attempt to provide a closed form of the solution, but they can only handle simple wire geometries. ...
... Traditional eff estimation techniques [5,6] focus on computing a single capacitance value for accurate gate delay estimation, thus being inadequate to approximate slew. To accurately estimate the nonlinear driver output waveform using CSMs, eff must be computed in multiple voltage regions [7]. ...
... More specifically, we develop two procedures for applying EKS-MM and AEKS-MM to large-scale regular and singular models, by implementing computationally efficient transformations in order to preserve the original form of the sparse input matrices. A preliminary version of this work appeared in [7]. Finally, we evaluate our methodology on industrial IBM power grids. ...
... The most widely used technique is Triple-Modular Redundancy (TMR), where fault tolerance is accomplished by triplicating the original module and inserting a two-out-of-three majority voting [7]. TMR may be utilised either for SEUs, and be applied at the FF level, or for SETs, and be applied to the most sensitive circuit gates [8], which critically affect circuit area and performance. Other possible approaches utilise three separate clock trees, with timing offset between them, or inserting a temporal filter at the TMR circuit structure [9], having significantly lower complexity and area cost. ...
... Gate-level timing analysis (i.e., STA [1] or DTA [19]) of VLSI circuits is performed in stages. First, the interconnect input admittance is approximated by eff and the driver output voltage waveform is computed in order to estimate driver delay and output slew. ...
... Finally, as can be seen in Eq. 5, matrix A is singular. This problem can be solved as described in [10] by eliminating the singularity of the original system. ...
... An integrated tool based on Monte-Carlo simulations, modeling the three masking phenomena (logical, electrical, and timing) that affect the probability that a transient fault will become a soft error and emphasizing on SEMTs analysis, is utilized for the SER evaluation process [26]. An SEMT occurs when a heavy ion strikes a sensitive area over the chip, producing glitches on adjacent cells. ...
... Both GB-STA and ED-DTA tools implement the Elmore and Composite Current Source (CCS) timing models for wire and gate delay estimation, respectively. Note that wire delay estimation can be improved by employing a more accurate interconnect timing analysis method [16]. GB-STA tool has also been extended to annotate the worst-case wire and gate delays in an SDF file, which is essential for GB-DTA. ...