N. Vasantha's research while affiliated with Vasavi College of Engineering and other places
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Publications (8)
One of the important block of BIST controller is LFSR and the speed with which BIST operates depends on LFSR systems design. There are methods in implementing LFSR using field programmable gate arrays (FPGAs) or digital signal processors (DSPs). BIST controller system speed is then limited to FPGAs and DSPs, which may influence other parameters suc...
The limitation with the existing testing techniques is, if the test does not consider all the aspects of SRAM parameters, including parasitic memory effect, then it will result as an incomplete test. This paper presents a new parasitic extraction testing method for embedded SRAMs, employing defect-induced layout. The defect injection in a circuit i...
A bit difficult task is to identify better fit algorithms for testing complex circuits such as SRAMs in the fast growing technology environment. Many fault models have emerged but limitations and constraints for the given test environment restrict their freedom of utilization. It is observed that majority of the existing fault models were analyzed...
With rapid increase in the use of embedded applications, the complex designs need huge amounts of on chip memory. The most preferred choice for high speed testing is the BIST. In this paper a decoder-adder design using low power Gate Diffusion Input (GDI) technique is proposed. The dynamic component of power is reduced, as the source of PMOS is not...
Border protection from intrusion has always been difficult and expensive, especially when the terrain is inhospitable. The paper proposes a new energy efficient approach to provide early detection of intrusion using Wireless sensor Networks. The systematically deployed sensor nodes not only detect the intrusion but also help to track them. The meth...
Citations
... Research in [10] removed a redundant read operation in the March C test sequence and reduced its complexity to 10N to become the March C-. Its complexity was further reduced to 8N in [14] by rearranging its test sequence into two concurrent subgroups that are executed in parallel. Somehow, they did not introduce any improvement to cover the undetectable DRDF and CFdrd. ...
... The steps involved in the proposed parasitic extraction method [15][16][17], are i) model the circuit with fault imposed ii) depends on the probability of occurrence, classify the fault types. iii) ext ract the defect induced layout from the fault model circuit iv) observe the defects in terms of short/open or missing of wires. ...
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... Defect based test analysis is more predominantly observed using fault location resistance and capacitance variations [9]. The fault locations were selectively chosen in the layouts and applied short or open defects for observing the faulty behaviors in the corresponding electrical circuit models [10][11][12][13][14][15][16][17][18][19][20][21]. Resistive-opens/shorts are generally coming under the category of timing-dependent fault models through which one can estimate the delay response of the circuit. ...
... (ii) The sensor nodes that have the mobility to roam around the surface area of the tunnel with maximised optimality and scalar sensor nodes that incorporated seismic or vibration sensors buried underground 8 . These three categories of sensor nodes need to be cooperative inside the underground tunnel for facilitating localisation capabilities that were not guaranteed by the existing underground patrolling systems [9][10][11][12][13][14] . ...
