N. S. S. Reddy’s scientific contributions

In this paper, a Fin FET 4:1Multiplexer utilizing 24 transistors has been proposed. The proposed Fin FET 24T 4:1 Multiplexer is developed utilizing in Cadence 18 nm innovation. The proposed outcomes are contrasted and the prior real structure. We have diminished two transistors by utilizing Morgan's laws contrasted and the prior real plan. Customary of Fin FET 4:1 Multiplexer utilizing 26 transistors as far as power, postponement and zone. It is played out the Dynamic power is diminished by 47.77%, Leakage Power is diminished 29.09% and Static Power is diminished by 14.61%. It is likewise understood that the postponement is diminished by 94.13% and territory is diminished by 40.74% for 24 transistors Fin FET 4:1Multiplexer in Cadence 18nm Technology.

This paper presents a low power adaptive LMS filter for filtering sine wave, square wave and sine-squarewaveforms which contains the noiseand to check how better the results are obtained after filtering. The Least Mean Square (LMS) algorithm used to process the signal in many DSP applications and filter uses the processed signal to generate further filter coefficients. Verilog HDL language is used to model the algorithm and synthesized using Xilinx ISE. Mentor Graphics Questasim tool is used to obtain the simulation results in the form of analog format. Due to adaptation of the coefficients, the proposed method reduces the power consumption. The power is calculated using Xilinx power estimator by targeting to FPGA.From the results, observed that adaptive filter efficiently working well for filtering noise from all types of waves like sine wave, square wave and sine-square wave signals. The observed results improved 46 % in area and 23 % in power consumption for the proposed system when compared to conventional FIR filter.

Adders are main component used in Digital signal processing (DSP) and are usually used in the digital integrated circuits. In Very-large-scale integration (VLSI) application delay, power and area are the necessary factors for any digital circuits. This paper presents 4 bit Carry Look ahead adder mapped in Cadence Encounter(R) RTL Compiler Version v14.20-s013_1. By efficiently mapping in cadence tool, area, power and delay are decreased. The results of mapping are viewed using RTL synthesis tool in cadence VIRTUOSO at 180 nm and 45nm technology, 1.8V and 0.7V. Based on digital signal processing (DSP) architectures, the code for low power is generated using 4 bit Carry Look ahead adder.

This present paper, a 3 transistor XNOR gate is proposed. The proposed XNOR gate is designed using CADENCE EDA tool and simulated using the SPECTRE VIRTUOSO at 180 nm technology. The proposed results are compared with the previous existing designs in terms of power and delay. It is observed that the power consumption is reduced by 65.19 % for three transistor XNOR gate and 48.11% for eight transistor full adder. It is also observed that the delay is reduced by 31.82% for three transistors XNOR gate and 28.76% for eight transistors full adder.

Now a days, low power Very Large Scale Integration (VLSI) circuit plays an important role in designing efficient energy saving electronic systems for high speed performance. In VLSI, low power dissipation is the main criterion in many electronic devices out of speed, area, etc., like mobile phones, laptops, high speed work stations etc., Due to the integration of many components on the VLSI circuit designs, power consumption is getting increased. Over a period, power management has become a major issue and challenging task for improving the battery life time and reducing the charging time in the electronic handheld devices. This paper presents five input Wallace tree and carry save adder are mapped into Cadence Encounter(R) RTL Compiler Version v14.20-s013_1. By efficiently mapping into cadence tool, area, power and delay are decreased. The results of mapping are viewed using RTL synthesis tool in cadence VIRTUOSO at 180 nm technology and 1.8V. Based on DSP architectures, the code for low power is generated using five input Wallace tree and carry save adder.