Muhammad S. Rashid’s research while affiliated with University of Bridgeport and other places

High performance packet switching networks are being deployed to provide sufficient data bandwidth for end users 3G services such as video streaming and broadband like data services. The use of high performance networks is, therefore, essential to the success of any 3G service. However, in practice, the deployment of High performance packet switching networks is hindered due to the improper congestion control which consequently results longer delays. In this paper, we propose a new method that can effectively improve the congestion control in high performance packet switching networks. Our numerical and simulation results demonstrate that the proposed method can be implemented for both lightly and heavily loaded networks. Simulation results show that the transmission delays can also be reduced significantly that improves the over all performance of high performance packet switching networks

As ATM network is designed for broad band transmission that is high data rate (25 Mbps to 2.5 Gbps) and supports the transmission of every kind of data, congestion control and delay have been important issues for ATM networks. Data transmission is done in the form of cell (53 bytes) relay. Hence, cell sequence and the error control have to be carried out properly. ATM networks presents difficulties in effectively controlling congestion not found in other types of networks, including frame relay networks. In this paper, we present an efficient methodology for traffic management. The simulation results suggest that the proposed solution is effective for both slow and high data rate transmission.

As ATM network is designed for broad band transmission that is high data rate (25 Mbps to 2.5 Gbps) and supports the transmission of every kind of data, congestion control and delay have been important issues for ATM networks. Data transmission is done in the form of cell (53 bytes) relay. Hence, cell sequence and the error control have to be carried out properly. ATM networks presents difficulties in effectively controlling congestion not found in other types of networks, including frame relay networks. In this paper, we present an efficient methodology for traffic management. The simulation results suggest that the proposed solution is effective for both slow and high data rate transmission.

New analytical and the speedup models for evaluating the performance of a generic reconfigurable coprocessor (RC) system are presented. We present a generic performance model for the speedup of a generic RC system. We demonstrate how different parameters of speedup model can affect the performance of reconfigurable system (RS). In addition, we implement our pre-developed speedup model for a system that permits preloading functional blocks (FB) into the reconfigurable hardware (RH). The redevelopment of speedup model with the consideration of preloading demonstrates some interesting results that can be used to improve the performance of RH with a coprocessor. Our experiments show that the minimum and the maximum speedup mainly depend on the probabilities of miss and hit for the FB resides in the RH of coprocessor. Index Terms—Field programmable gate array, reconfigurable coprocessors, reconfigurable hardware.