Mohammad Madihian’s research while affiliated with Agency for Science, Technology and Research (A*STAR) and other places

In this paper, on-chip higher-order-mode dielectric-resonator antennas (DRAs), fed by a half-mode-backed cavity structure using standard CMOS technology, are presented. With the dominant cavity mode (half-TEz100), the half-mode cavity-feeding structure provided a high antenna radiation efficiency. The dielectric resonators (DRs) were designed to operate at higher-order modes (TEx¿¿13, TEx¿¿15) to enhance the antenna gain. At around 135 GHz, the proposed antennas demonstrated measured gains of 6.2 dBi and 7.5 dBi for the TEx¿¿13 and TEx¿¿15 modes, respectively, with corresponding simulated radiation efficiencies of 46% and 42%. Both antennas had a measured impedance bandwidth of 7%. The proposed antennas not only accomplished high gain without occupying a large chip area, but also maintained comparable or even improved cost performance and simplicity over other on-chip antennas.

This study describes a class of D-band hybrid couplers employing a structurally improved phase inverter in a standard CMOS technology. The proposed phase inverter, which consists of an inverter core and two quasi-parallel striplines along with two slots for impedance matching improvement, is characterised by an equivalent circuit model to facilitate the design procedure. A 180° coupler deploying the phase inverter features 38% size reduction and over 60% bandwidth improvement compared with its conventional counterparts. The proposed rat-race coupler achieves an insertion loss of around 1.1 and 30 dB isolation bandwidth of over 31 GHz, with a peak isolation of 41 dB at 118 GHz. A 90° coupler using the phase inverter demonstrates a return loss and isolation of 14 and 18 dB, respectively, in the whole D-band range. The measured amplitude and phase imbalances for the broadband coupler are, respectively, within 1 dB and 6° from 110 to 160 GHz. Both couplers can be inherently integrated with millimetre-wave circuits for on-chip system applications.

This brief proposes a guard ring using through-silicon vias (TSVs) to isolate thermal coupling in a 3-D integrated circuit (3-D IC). To verify this idea, simulation and measurement are carried out. A ring oscillator (RO) is implemented in a 65-nm CMOS and then measured in four different conditions. The results show that, without affecting the inherent electrical performance of the RO, the designed TSV ring shields the RO from high-temperature environments. The oscillation frequency shifting is mitigated from 5.96 MHz without TSV to 2.11 MHz with the proposed TSV ring. This TSV-based structure provides a good option to alleviate thermal coupling in a highly integrated 3-D IC.

In this paper, an ultra-low-energy biomedical signal processor (BSP) is proposed for wireless multi-channel physiological signal monitoring. This BSP integrates a RISC core and application-specific hardware accelerators (ASHAs) to achieve ultra low power consumption while meeting required performance. Various low power design techniques from system to circuit levels are applied, including event-driven signal processing, dynamic clock management, near-threshold operation, glitch-free clock generation, fine-grain clock gating, and ultra-low-voltage level shifting. The BSP can operate with supply from 1.8V down to 0.5V. With integrated ECG ASHAs based on the discrete wavelet transform, its overall energy consumption is 20.4pJ/cycle at 0.5V and 10MHz when performing a real-time wireless ECG monitoring.

In this paper, a six-port distributed model of on-chip single-turn transformers in silicon that can predict the features of the transformers up to 200 GHz is presented. Moreover, the proposed model is scalable with the diameter of the transformer. Based on the developed model, a transformer balun with improved differential-port balance is deployed in a D-band up-conversion mixer design in 0.13-μm SiGe BiCMOS technology. The mixer achieves a measured conversion gain (CG) of 4 ~ 7 dB and local-oscillator-to-RF isolation over 30 dB from 110 to 140 GHz. The results have one of the best CGs in the millimeter-wave range. A D-band two-stage transformer-coupled power amplifier (PA) integrated with a mixer is also reported here. Using the six-port transformer model, the performance of the PA can be conveniently optimized. At a 2-V supply, the gain and saturated output power of 20 dB and 8 dBm, respectively, are both experimentally achieved at 127 GHz. At 3 V, the measured output power rose to 11 dBm and this is the best power performance among the reported D-band silicon-based amplifiers to date.

This paper presents a terahertz (THz) transmitter (Tx) and receiver (Rx) chipset operating around 400 GHz in 0.13- μm SiGe BiCMOS technology. The Tx chip consists of a voltage-controlled oscillator, a buffer, a modulator, a power amplifier, a frequency tripler, and a substrate integrated waveguide (SIW) antenna. This antenna has an additional high-pass filtering characteristic to suppress the unwanted fundamental (f0) and second harmonic (2f0) signals by 50 and 30 dB, respectively. The Rx chip includes a proposed reconfigurable SIW antenna and a novel two-mode subharmonic mixer with ~ 5-dB reduction of conversion loss. The Rx chip consumes 50 nA from a 1.2-V supply. The measurement results of the Tx and Rx chips and a back-to-back test of the Tx/Rx chipset show the feasibility and pave the way of implementing a fully integrated THz system in silicon technology for mass production.

This work discusses the design methodologies of 130-GHz high gain and high efficiency on-chip meander slot antennas in a standard CMOS technology. In the proposed structure, stacked dielectric resonators (DRs) are placed on the top of the on-chip feeding element to form series-fed antenna array for antenna gain and efficiency improvement. The integrated antenna with double stacked DRs achieved a measured gain of 4.7 dBi at 130 GHz with a bandwidth of 11%. The antenna size is 0.8 ×0.9 mm2 and the simulation results indicate a radiation efficiency of 43%. To the best of our knowledge, this is the first demonstration of an on-chip antenna gain and efficiency enhancement through stacked DRs.

In this paper, a D-band on-chip dielectric resonator antenna (DRA) fed by a half-mode backed cavity structure using a standard CMOS technology is presented. The half-mode cavity feeding structure in the proposed antenna permits easy excitation of both the dominant modes of the cavity (half-TEz110) and the dielectric resonator (TExε11). Based on this technology, a 135-GHz antenna is demonstrated, with a measured impedance bandwidth of 13% and a peak gain of up to 3.7 dBi at 132 GHz. Moreover, the radiation efficiency is simulated to be 62%. The chip size is 0.7 × 0.9 mm2 including the test pad. The proposed antenna is able to maintain comparable radiation performance of the off-chip antennas and has the advantage of easy integration with active circuits and also low cost.

This paper presents a 2.45-GHz wireless link to power on the miniaturized biomedical devices. In this link, a chip antenna is adopted for RF power transmitting, and a resonant network consisting of a compact inductor and a chip capacitor is employed for energy harvesting. A prototype is fabricated and measured in the time- and frequency-domain. The measured results show that this power transfer link meets the system requirement. In addition, in the case of a capacitor with 20% variation, this link can still achieve the system required efficiency. It therefore eliminates the adaptive matching circuit and simplifies the system design.

This paper presents a broadband inductor-less variable gain amplifier (VGA) with a linear-in-dB gain control characteristic and DC-offset cancellation. The proposed VGA is composed of a variable gain block, an exponential voltage generator, a DC-offset canceller with common-mode voltage correction, and a gain peaking block. To achieve the broad band and reduce the chip area, the gain peaking block employs an inductor-less gain peaking scheme to compensate the high frequency gain drop of the variable gain block and the DC-offset canceller. The VGA fabricated in 0.13 μm SiGe BiCMOS technology achieves a 3-dB bandwidth of 7.5 GHz and a variable gain range from −10 to 30 dB. Due to the inductor-less design, the die area is only 0.53 × 0.27 mm2 which is the smallest among other similar reported works. At 10-Gb/s, the VGA consumes 50 mW power from a single 1.2 V supply and exhibits an output data jitter of less than 30 pspp.