Mathys Walma’s research while affiliated with Intel and other places

Traditional methods to calculate CRC suffer from diminishing returns. Doubling the data width doesn't double the maximum data throughput, the worst case timing path becomes slower. Feedback in the traditional implementation makes pipelining problematic. However, the on chip data width used for high throughput protocols is constantly increasing. The battle of reducing static power consumption is one factor driving this trend towards wider data paths. This paper discusses a method for pipelining the calculation of CRC's, such as ISO-3309 CRC32. This method allows independent scaling of circuit frequency and data throughput by varying the data width and the number of pipeline stages. Pipeline latency can be traded for area while slightly affecting timing. Additionally it allows calculation over data that isn't the full width of the input. This often happens at the end of the packet, although it could happen in the middle of the packet if data arrival is bursty. Finally, a fortunate side effect is that it offers the ability to efficiently update a known good CRC value where a small subset of data in the packet has changed. This is a function often desired in routers, for example updating the TTL field in IPv4 packets.

This paper discusses a method for pipelining the calculation of CRC's, such as ITU/CCITT CRC32, into a mostly feed-forward architecture. This method allows several benefits such as independent scaling of circuit frequency and data throughput. Additionally it allows calculation over packet tails (packet length not a multiple of CRC input width). Finally it offers the ability to update a CRC where a subset of data in the packet has changed.