Martin Izzard's research while affiliated with Palo Alto Networks and other places

Publications (8)

Article
Full-text available
OpenFlow is a vendor-agnostic API for controlling hardware and software switches. In its current form, OpenFlow is specific to particular protocols, making it hard to add new protocol headers. It is also tied to a specific processing paradigm. In this paper we make a strawman proposal for how OpenFlow should evolve in the future, starting with the...
Conference Paper
In Software Defined Networking (SDN) the control plane is physically separate from the forwarding plane. Control software programs the forwarding plane (e.g., switches and routers) using an open interface, such as OpenFlow. This paper aims to overcomes two limitations in current switching chips and the OpenFlow protocol: i) current hardware switche...
Conference Paper
In Software Defined Networking (SDN) the control plane is physically separate from the forwarding plane. Control software programs the forwarding plane (e.g., switches and routers) using an open interface, such as OpenFlow. This paper aims to overcomes two limitations in current switching chips and the OpenFlow protocol: i) current hardware switche...
Article
Full-text available
In this paper, we present the Tiny Tera: a small packet switch with an aggregate bandwidth of 320Gb/s. The Tiny Tera is a CMOS-based input-queued, fixed-size packet switch suitable for a wide range of applications such as a highperformance ATM switch, the core of an Internet router or as a fast multiprocessor interconnect. Using off-the-shelf techn...
Article
In this paper, we present the Tiny Tera: a small packet switch with an aggregate bandwidth of 320Gb/s. The Tiny Tera is a CMOS-based input-queued, fixed-size packet switch suitable for a wide range of applications such as a high- performance ATM switch, the core of an Internet router or as a fast multiprocessor interconnect. Using off-the-shelf tec...
Article
Contents Introduction .................................................................................. 3 Objectives ...................................................................................... 4 Technical Background ................................................................. 4 3.1 Input vs. Output Queueing ...........................
Article
Describes Tiny Tera: a small, high-bandwidth, single-stage switch. Tiny Tera has 32 ports switching fixed-size packets, each operating at over 10 Gbps (approximately the Sonet OC-192e rate, a telecom standard for system interconnects). The switch distinguishes four classes of traffic and includes efficient support for multicasting. We aim to demons...
Article
The tiny tera is an all-CMOS 320 Gbps, input-queued ATM switch suitable for non-ATM applications such as the core of an Internet router. The tiny tera efficiently supports both unicast and multicast traffic. Instead of using optical switching technology, we achieve a high switching-bandwidth by using less expensive and proven CMOS technology. Becau...

Citations

... Another major trend that we have seen in the recent years is that with the rise of software-defined networks [36], switches and network cards have become programmable [10,51] and thus turned networks from being passive to being active. This programmability of the network opens up many additional opportunities to tailor the network to the applications on top. ...
... We also introduce a new primitive, reset, which models the behavior of P4 between pipeline stages. In many switch architectures [Bosshart et al. 2013], packets are deparsed and then reparsed between pipelines-e.g., after ingress and before egress. The reset command encodes the behavior of the inner step: it combines the deparsed bits with the packet's unparsed payload and passes it along as the input to the next stage. ...
... In addition, MATReduce [30] merges duplicate match operations between different P4 [31] match-action tables to accelerate the packet processing pipeline of P4 switches. However, MATReduce only targets P4 switches so it lacks necessary factors for SFC implementation, such as maintaining NF dependencies. ...
... The Internet has continued its explosive growth supported by the rapid progress of related technologies. State-of-the-art IP routers and ATM switches (key devices for the Internet) have tens of gigabits per second throughput and will have hundreds of gigabits or one terabits per second throughput early in the next century [1]. However, it seems very difficult to keep increasing the throughput if we use only electronic technologies because of their inherent physical limitations Manuscript received September 11, 1998. ...
... This coordination mechanism depends on the structure of the switch cache. At present, many researchers have done a lot of research on the problem of switch cache structure [27,28]. In this paper, the buffer of the bmv2 switch is shared among all ports. ...
... Numerous proposals for identifying suitable architecture for high-performance packet switches have been investigated and implemented both in academia and industry [1], [2], [3], [4]. These architectures can be classified based on various attributes such as queuing schemes, scheduling algorithms, and/or switch fabric topology. ...