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October 2007
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45 Reads
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37 Citations
We consider dynamic power dissipation in FPGAs and present CAD techniques for dynamic power reduction. The proposed techniques, comprising power-aware placement, routing, and a novel post-routing transformation, are applied to optimize the power consumed by industrial designs implemented in the Xilinxreg Virtextrade-5 FPGA. Board-level power measurements on a suite of industrial designs show that the techniques reduce power by 10%, on average.
... In [1] power consumption in 65nm FPGA is tested by the authors which has given a benefit in low power consumption than Virtes-4 FPGA. In [2] authors have designed CAD technique for power optimization. In this work they have tried to reduce the dynamic power dissipitation. ...
October 2007
