Lennart Weingarten’s research while affiliated with University of Bremen and other places

The use of Boolean Satisfiability (SAT) solver for hardware verification incurs exponential run-time in several instances. In this work we have proposed an efficient quantum SAT (qSAT) solver for equivalence checking of Boolean circuits employing Grover’s algorithm. The Exclusive-Sum-of-Product (ESOP)-based generation of the Conjunctive Normal Form (CNF) equivalent clauses demands less qubits and minimizes the gates and depth of quantum circuit interpretation. The consideration of reference circuits for verification affecting Grover’s iterations and quantum resources are also presented as a case study. Experimental results are presented assessing the benefits of the proposed verification approach using open-source Qiskit platform and IBM quantum computer.

Verification plays a major role in ensuring the functional correctness of any design. In recent years with growing complexity of processor designs, verification has assumed utmost importance. Simulation-based techniques cannot ensure completeness in verification, and in this regard formal methods prove crucial. Although formal methods guarantee completeness it is hard to quantify the exact time and space complexities. Recently some works have demonstrated that it is possible to achieve polynomial space and time complexities for various arithmetic circuits as well as for processors. In this paper we propose a Binary Decision Diagram (BDD) based Polynomial Formal Verification (PFV) approach for verifying processors. As a case study, we discuss the PFV for a multi-cycle processor (viz., MicroRV32) with support for combinational and sequential sub-systems. New data structures and code base are utilized to verify all the functional components. Experimental results reveal that the verification can indeed be performed in polynomial time.

The use of Boolean Satisfiability (SAT) solver for hardware verification incurs exponential run-time in several instances. In this work we have proposed an efficient quantum SAT (qSAT) solver for equivalence checking of Boolean circuits employing Grover's algorithm. The Exclusive-Sum-of-Product based generation of the Conjunctive Normal Form equivalent clauses demand less qubits and minimizes the gates and depth of quantum circuit interpretation. The consideration of reference circuits for verification affecting Grover's iterations and quantum resources are also presented as a case study. Experimental results are presented assessing the benefits of the proposed verification approach using open-source Qiskit platform and IBM quantum computer.

The size and the complexity of digital circuits are increasing rapidly. This makes the circuits highly error-prone. As a result, proving the correctness of a circuit is of utmost importance after the design phase. Arithmetic circuits are among the most challenging designs to verify due to their high complexity and big size. In recent years, several formal methods have been proposed to verify arithmetic circuits. However, time and space complexity bounds are still unknown for most of these approaches, resulting in performance unpredictability. In this paper, we clarify the importance of polynomial formal verification for digital designs particularly arithmetic circuits. We also introduce an Arithmetic Logic Unit (ALU) and prove that formal verification of this circuit is possible in polynomial time. Finally, we confirm the correctness of the complexity bounds by experimental results.KeywordsFormal verificationComplexityPolynomialArithmetic circuitsArithmetic logic unitBinary decision diagram