Lei Wang's research while affiliated with Academy of Military Medical Sciences and other places
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Publications (12)
Binaural Sound Source Localization (BSSL) is a remarkable topic in robot design and human hearing aid. A great number of algorithms flourished due to a leap in machine learning. However, prior approaches lack the ability to make a trade-off between parameter size and accuracy, which is a primary obstacle to their further implementation on resource-...
For the purpose of fixing timing violations, static timing analysis (STA) of full-corners is repeatedly executed, which is time-consuming. Given a timing path, timing results at some corners (“dominant corners”) are utilized to predict timing at other corners (“non-dominant corners”), which can greatly shorten the runtime of STA. However, the huge...
Programmers sometimes need to use some methods they are not familiar with like methods from other projects or written by others. However, it is hard to obtain usage information of a general method that is not a commonly used API or in the project with high impact, since this method may only have a brief comment and several usage examples. In this p...
High Efficiency Video Coding (HEVC) is a new international video compression standard offering much better compression efficiency than previous video compression standards at the expense of much higher computational complexity. This paper presents a design of two-dimensional (2D) discrete cosine transform (DCT) hardware architecture dedicated for H...
Spiking neural network (SNN) trained by spike-timing-dependent plasticity (STDP) is a promising computing paradigm for energy-efficient artificial intelligence systems. During the learning procedure of SNN trained by STDP,
another two bio-inspired mechanisms of lateral inhibition and homeostasis are usually implemented to achieve competitive learni...
Floorplan is an important process whose quality determines the timing closure in integrated circuit (IC) physical design. And generating a floorplan with satisfying timing result is time-consuming because much time is spent on the generation-evaluation iteration. Applying machine learning to the floorplan stage is a potential method to accelerate t...
Determining the optimal microarchitecture configuration of a processor at the early stages of design is undeniably a challenge. Due to many parameters at the microarchitecture level, finding the proper combination of these parameters to arrive at a balanced design is difficult. Application-specific Design Space Exploration (DSE) is even more diffic...
The Discrete cosine transform (DCT) and inverse Discrete cosine transform (IDCT) have been widely used in image and video compression standards, and more and more researchers focus on the method that taking use of the coordinate rotation digital computer (CORDIC) to execute the DCT and IDCT, the reason is that CORDIC can realize the complex transce...
Citations
... The intuition is that the timing result of all corners lives in a low-dimensional ambient space and thus can be reconstructed using timing results under some corners by harnessing the correlation under all corners. Following the same assumption, Zhao et al. [15] put forth nonlinear regression models for the STA prediction with improved accuracy. Also, they propose using a statistical analysis tool to pick key STA results (referred to as dominating process corners) as model inputs to save extra STA executions while maintaining a good predictive accuracy. ...
... Over the past several years, machine learning (ML) algorithms have been widely utilized in chip design for their potential to enhance design quality, reduce runtime costs, and achieve no human-in-the-loop process [1][2][3][4][5][6][7]. ML algorithms, especially recent deep learning (DL) algorithms [8][9][10][11] and reinforcement learning (RL) algorithms [12,13], have been extensively explored to address various problems encountered in chip design, such as high-level synthesis (HLS) [14][15][16][17][18][19][20][21][22][23][24], floorplanning [25][26][27][28][29][30][31][32][33][34][35][36][37], placement , and routing [62][63][64][65][66][67][68][69]. Despite the abundance of research in this area, there remains a lack of clear links between the ML algorithms and the target problems in chip design, causing a huge gap in understanding the potential and possibility of ML in future chip design. ...
... In another work, Querlioz et al. [33] performed unsupervised learning with memristive STDP synapses, and achieved a simulation accuracy of 93.5% with 300 output neurons. Several other works [34,[40][41][42][43] have also tested SNNs, using memristive synapses. Table 1 lists the related memristive STDP studies, along with their memristive material choices (where applicable), their customised synaptic learning rule, their image pre-processing techniques, as well as the number of training epochs they have used. ...
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... Motivated by this increasing demand, we focus our work on further reducing the arithmetic complexity of the DCT computation, which directly affects hardware-oriented measures such as chip area, dynamic power consumption, critical path delay, gate-count, area-time, and maximum clock frequency (throughput) [42,[80][81][82][83][84][85]. ...
