Lasse Södergren’s research while affiliated with Lund University and other places

In current quantum computers, most qubit control electronics are connected to the qubit chip inside the cryostat by cables at room temperature. This poses a challenge when scaling the quantum chip to an increasing number of qubits. We present a lateral nanowire network 1-to-4 demultiplexer design fabricated by selective area grown InGaAs on InP, suitable for on chip routing of DC current for qubit biasing. We have characterized the device at cryogenic temperatures, and at 40 mK the device exhibits a minimum inverse subthreshold slope of 2 mV/dec, which is encouraging for low power operation. At low drain bias, the transmission breaks up into several resonance peaks due to a rough conduction band edge; this is qualitatively explained by a simple model based on a 1D real space tight-binding nonequilibrium Green's functions model.

We present electronic band structure properties of strained In x Ga (1− x ) As/InP heterostructure near surface quantum wells oriented in the (100) crystallographic direction using eight-band [Formula: see text] theory, which are further parameterized by an energy level, effective mass, and nonparabolicity factor. The electronic band structure parameters are studied for the well composition of 0.2 ≤ x ≤ 1 and thickness from 5 to 13 nm. The bandgap and effective mass of the strained wells are increased for x >0.53 due to compression strain and decreased for x < 0.53 due to tensile strain as compared to that of unstrained wells. The calculated band structure parameters are utilized in modeling long channel In 0.71 Ga 0.29 As/InP quantum well MOSFETs, and the model is validated against measured I–V and low frequency C–V characteristics at room temperature and cryogenic temperature. Exponential band tails and first- and second-order variation of the charge centroid capacitance and interface trap density are included in the electrostatic model. The Urbach parameter obtained in the model is E 0 = 9 meV, which gives subthreshold swing (SS) of 18 mV/dec at T = 13 K and agrees with the measured SS of 19 mV/dec. Interface trap density is approximately three orders higher at T = 300 K compared to T = 13 K due to multi-phonon activated traps. This model emphasizes the importance of considering disorders in the system in developing device simulators for cryogenic applications.

Monolithic integration of III-V semiconductors with Silicon technology has instigated a wide range of new possibilities in the semiconductor industry, such as the combination of digital circuits with optical sensing and high-frequency communication. A promising CMOS compatible integration process is Rapid Melt Growth (RMG) that can yield high quality single crystalline material at a low cost. This paper represents the study on ultra-thin InSb-on-Insulator microstructures integrated on a Si platform by a RMG-like process. We utilize Flash Lamp Annealing (FLA) to melt and recrystallize the InSb material for an ultra-short duration (milliseconds), to reduce the thermal budget necessary for integration with Si technology. We compare the result from FLA to regular Rapid Thermal Annealing (seconds). Recrystallized InSb was characterized using Electron Back Scatter Diffraction which indicates a transition from nanocrystalline structure to a crystal structure with grain sizes exceeding 1 µm after the process. We further see a 100x improvement in electrical resistivity by FLA annealed sample when compared to the as-deposited InSb with an average Hall mobility of 3100 cm2/Vs making this a promising step towards realizing monolithic mid-infrared detectors and quantum devices based on InSb.

In this paper an optimized process flow of near‐surface quantum well MOSFETs (metal oxide semiconductor field effect transistors) based on planar layers of MOVPE (metalorganic vapor‐phase epitaxy) grown InxGa1‐xAs is presented. It is found that by an optimized pre‐growth cleaning and post metal anneal the quality of the MOS structure can be greatly enhanced. This optimization is a first step towards realization of a scalable platform for topological qubits based on a well‐defined network of lateral InxGa1‐xAs nanowires grown by selective area growth. This article is protected by copyright. All rights reserved.

Laterally grown InxGa1xAs nanowires (NWs) are promising candidates for radio frequency and quantum computing applications, which, however, can require atomic scale surface and interface control. This is challenging to obtain, not least due to ambient air exposure between fabrication steps, which induces surface oxidation. The geometric and electronic surface structures of InxGa1xAs NWs and contacts, which were grown directly in a planar configuration, exposed to air, and then subsequently cleaned using atomic hydrogen, are studied using lowtemperature scanning tunneling microscopy and spectroscopy (STM/S). Atomically flat facets with a root mean square roughness of 0.12 nm and the InGaAs (001) 4 2 surface reconstruction are observed on the top facet of the NWs and the contacts. STS shows a surface bandgap variation of 30 meV from the middle to the end of the NWs, which is attributed to a compositional variation of the In/Ga element concentration. The well-defined facets and small bandgap variations found after area selective growth and atomic hydrogen cleaning are a good starting point for achieving high-quality interfaces during further processing.

In this work, we study the electron mobility of near surface metal organic vapor phase epitaxy-grown InGaAs quantum wells. We utilize Hall mobility measurements in conjunction with simulations to quantify the surface charge defect density. Buried quantum wells are limited by polar optical phonon scattering at room temperature. In contrast, the quantum wells directly at the surface are limited by remote charge impurity scattering from defects situated at the III–V/oxide interface or inside the oxide, showing a mobility of 1500 cm²/V s. Passivating the InGaAs surface by depositing an oxide reduces the amount of defects at the interface, increasing the mobility to 2600 cm²/V s.

We present a semi self-aligned processing scheme for III–V nanowire transistors with novel semiconductor spacers in the shape of Λ-ridges, utilising the effect of slow growth rate on {111}B facets. The addition of spacers relaxes the constraint on the perfect alignment of gate to contact areas to enable low overlap capacitances. The spacers give a field-plate effect that also helps reduce off-state and output conductance while increasing breakdown voltage. Microwave compatible devices with Lg = 32 nm showing fT = 75 GHz and fmax = 100 GHz are realized with the process, demonstrating matched performance to spacer-less devices but with relaxed scaling requirements.