Larysa Titarenko’s research while affiliated with University of Zielona Góra and other places

A new state assignment method focusing on Mealy finite state machines (FSMs) is proposed. The proposed codes are an alternative to composite state codes (CSCs). CSCs are represented as concatenations of group codes and partial state codes. Both group and partial state codes are maximum binary codes. We propose encoding groups using one-hot codes. The main goal of this method is improving the value of the FSM cycle time without a significant degradation of the spatial characteristics. The method can be applied if FSM circuits are implemented using the look-up table (LUT) elements of field-programmable gate arrays (FPGAs). The resulting FSM circuit includes three logic blocks. The first block generates partial input memory functions and FSM outputs depending on maximum binary state codes and one-hot group codes. The partial codes are assigned in a way minimizing the number of arguments in the partial functions. This allows for the generation of most partial functions by single-LUT circuits. The second block generates the final values of the input memory functions and FSM outputs. This block does not require group codes to generate functions, as in CSC-based FSMs. The third block transforms maximum binary group codes into their one-hot equivalents. The proposed approach allows for a reduction in the number of series-connected LUTs in comparison with CSC-based FSMs. Due to this reduction, the temporal characteristics of an FSM circuit are improved. This paper includes an example of FSM synthesis applying the proposed method. The experiments were conducted using standard benchmark FSMs. The results of the experiments show that the proposed method allowed for an improvement in the cycle time of an average of 8.81%. Moreover, in relation to CSC-based FSMs, the LUT counts decreased by an average of 4.00%.

In this paper, we proposed a new state assignment method focusing on Mealy finite state machines (FSMs). The method makes it possible to improve the temporal characteristics of the circuits of FSMs, the internal states of which are encoded by the composite state codes (CSCs). These codes consist of class codes and partial state codes. Both class and partial state codes are maximum binary codes. We propose to encode classes by one-hot codes. The main goal of the method is improving the value of the FSM cycle time without any significant degradation of spatial characteristics. The method can be applied if FSM circuits are implemented using look-up table (LUT) elements of field-programmable gate arrays (FPGAs). The resulting FSM circuit includes two logic blocks. The first block generates partial input memory functions and FSM outputs depending on maximum binary state codes and one-hot class codes. The choice of partial codes allows minimizing the systems of partial functions. This allows generating most partial functions by single-LUT circuits. Some partial functions require using dedicated multiplexers. The second block generates final values of input memory functions and FSM outputs. This block does not require class codes to generate functions, which is the case of CSC-based FSMs. The proposed approach allows reducing the number of series-connected LUTs in comparison with CSC-based FSMs. Due to this reduction, the temporal characteristics are improved. The paper includes an example of FSM synthesis through applying the proposed method. The experiments are conducted using standard benchmark FSMs. The results of experiments show that the proposed method allows improving the temporal characteristics (by an average of 9.15%). In relation to CSC-based FSMs, the number of LUTs increases by an average of 10.03%, and the power consumption increases by an average of 7.63%.

Introduction. The control unit is the most important block of digital systems. Unlike other blocks, the control unit generates signals in each cycle of the system and therefore consumes a significant amount of electrical power. Currently, the problem of reducing power consumption is of particular importance. FPGA (field-programmable logic array) chips are widely used in the implementation of various digital systems. According to experts, these chips will be widely used in the design of digital devices for several decades to come. This factor determines the choice of this particular element basis. The proposed method is focused on FPGA, which is manufactured by AMD Xilinx. This choice is due to the company's leading position in the FPGA chip market. The purpose of the article. One of the ways to reduce power consumption is to regularize the control device circuit and reduce the number of connections between its elements. This article proposes a solution to this problem when implementing composite microprogrammed control device (CMCD) circuits in the FPGA basis. The following FPGA chip resources are used to implement the CMCD circuit: elements of the LUT (look-up table) type, embedded memory blocks (EMB) and programmable interconnections. The main idea of the proposed method is to adapt the method of double coding of states to the features of the CMCD with the basic architecture. The analogs of the states are the CMCD microinstructions. Therefore, optimization is achieved due to double addressing of microinstructions. Results. The proposed method allows to obtain a CMCU circuit with a regular structure. The regularity consists in the fact that: logical conditions are associated only with the elements of the first level, synchronization signals are associated only with the second level of the circuit; any partial function is a circuit consisting of one LUT element. Analysis of the circuits of microprogrammed machines with double coding of states shows that regular circuits have a number of advantages over circuits based on functional decomposition: a smaller number of LUT elements and interconnections, a higher frequency of synchronization pulses (high speed), a lower value of consumed power. Conclusions. The proposed method is appropriate to use in cases where, due to the small number of inputs of the LUT elements of FPGA circuits, known methods require the use of functional decomposition, which leads to circuits with an irregular structure and a complex interconnection system. Such circuits have low performance and consume a lot of energy. Keywords: composite microprogrammed control device, LUT, EMB, synthesis.