Kyoungchoul Koo’s research while affiliated with Samsung and other places

In this paper, a model of power supply noise (PSN) effects on an analog-to-digital converter (ADC) in a hierarchical structure is proposed. The ADC performance is determined by not only on-chip characteristics but also off-chip characteristics. Therefore, chip-package-printed circuit board (PCB) coanalysis and comodeling are required to accurately evaluate the performance of the ADC. We propose the comodel which allows the estimation and analysis of PSN effects on the ADC including off-chip characteristic. The proposed model includes three separate submodels: a power distribution network (PDN) model from the power/ground of the PSN source to the ADC power/ground, an on-chip circuit model from the ADC power/ground to the ADC inputs, and an ADC behavioral model from the ADC inputs to the factor of the effective number of bits (ENOB), which is one of the ADC performance factors. By applying a segmentation method for the PDN model, an analytical model for the on-chip circuit model, and a MATLAB model for the ADC behavioral model, fast, precise, and broadband estimations of the PSN effects are achieved. To validate the proposed models, an ADC was fabricated by a 0.13-μm CMOS process and wire bonded to the designed PCB. The ENOB of the ADC was measured by sweeping the PSN's frequency from 1 MHz up to 3 GHz, which was injected into the PCB to discover which noise frequency is critical to an ADC designed with a chip-PCB hierarchical structure. The results estimated by the proposed model correlated well with the cosimulated and measured results. The proposed modeling procedure saves the chip, package, and PCB designers time and computation resources to achieve high-quality analog devices or mixed-mode systems and provides an intuitive understanding of the noise effect.

In this paper, a new decoupling capacitor stacked chip (DCSC) based on extra decoupling capacitors and through-silicon-vias (TSVs) is proposed to overcome the narrow-bandwidth limitation of the conventional decoupling capacitor solutions in three-dimensional-integrated circuits (3-D-ICs), as exhibited by expensive on-chip metal-oxide-semiconductor (MOS) decoupling capacitors and inductive off-chip discrete decoupling capacitors. In particular, in comparison to the on-chip decoupling solutions, such as MOS, metal-insulator-metal and deep trench capacitors, the proposed TSV-based DCSC represents several advantages, such as small leakage currents, large capacitances ranging from tens of nF to a few μF, low equivalent series inductance (ESL) with tens of pH, and high flexibility in TSV arrangements. The proposed TSV-based DCSC can be applied by mounting decoupling capacitors, such as Si-based MOS capacitors and discrete capacitors, on the backside of a chip and connecting the capacitors to the on-chip power delivery network (PDN) through TSVs. To demonstrate the performance of the proposed DCSC structure, a segmentation method was applied to compare the PDN impedance (Z11) of the TSV-based DCSC with those of the well-known conventional decoupling capacitor methods. The TSV-based DCSC was found to exhibit the advantages of both low on-chip level ESL (under several tens of pH) and high off-chip level capacitance (up to several μF). Additionally, the PDN impedance properties of the TSV-based DCSC were analyzed with respect to the variations in the number of power/ground TSV pairs, on-chip PDN size, and capacitance values of the stacked off-chip discrete decoupling capacitors using the segmentation method.

In this paper, we propose a vertical stepped impedance electromagnetic bandgap (VSI-EBG) structure with a stopband enhancement and a size reduction for a wideband suppression of simultaneous switching noise (SSN) coupling in multilayer printed circuit boards (PCBs). The proposed VSI-EBG structure forms the stepped impedance EBG structure of power planes, which is implemented with a vertical branch, high-impedance (hi-Z) and low-impedance (low-Z) metal patches on different layers. Test vehicles are fabricated using a multilayer PCB process to verify the proposed VSI-EBG structure. Through experimental measurements, we verified the enhanced suppression of SSN coupling (below -40 dB) between 650 MHz and 20 GHz. In addition, we demonstrated that fL is reduced from 2.4 GHz to 650 MHz compared to the previous EBG structure, which allows an approximately 86% size reduction.

In this paper, we propose a fast and accurate model of the vertical noise coupling from an on-chip switching-mode power supply (SMPS) to a low noise amplifier (LNA) in a stacked 3-D-IC. To achieve both speed and accuracy, the model is based on the analytic formulas of static R, L, and C parasitic extraction, and includes consideration of the phase difference in the on-chip inductors using a new iterative calculation method. The proposed model and the prediction of vertically coupled noise at the LNA output using the model are experimentally validated on a fabricated stacked 3-D-IC consisting of an onchip SMPS and LNA. Good agreement with the measurements is confirmed in both the frequency domain and the time domain. The enhancements of the proposed model, including the broad model bandwidth (<; 4 GHz) as good as 3-D EM solver and 99% reduction of the simulation elapsed time (2 s) from 3-D EM solver, are confirmed. This paper also analyzes: 1) the impact of vertical noise coupling on the RF signal gain performance of the LNA and 2) the impact of variation in the stacking configuration, location, and thickness of the stacked LNA on the vertical noise coupling using the proposed model. Based on the results of our analysis, this paper proposes and verifies an effective method to reduce the vertical noise coupling using the proposed model.

In this paper, we propose a model for 3-D stacked on-chip power distribution networks (PDNs) in through silicon via (TSV)-based 3-D memory ICs that includes the effects of power/ground TSVs (P/G TSVs), on-chip decoupling capacitors (on-chip decaps), and the silicon substrate. In the modeling procedure of 3-D stacked on-chip PDNs, the distributed RLGC-lumped model of an on-chip PDN, including the effects of the on-chip decaps and silicon substrate, is proposed. Additionally, the RLGC-lumped model of a P/G TSV pair is introduced. The proposed model of the 3-D stacked on-chip PDN combines the proposed models of on-chip PDNs with the models of P/G TSV pairs in a hierarchical order with a segmentation method. The proposed models of the on-chip PDN and 3-D stacked on-chip PDN are successfully validated by simulations and measurements up to 20 GHz. Additionally, with these models, the impedances of the 3-D stacked on-chip PDNs are analyzed with respect to the variations in the number of P/G TSV pairs, the capacitance of on-chip decaps, and the height of an interlayer dielectric layer between the on-chip PDN and silicon substrate. These variations critically affect the impedance of the 3-D stacked on-chip PDN by changing the capacitance and inductance of the PDN.

Vertical noise coupling caused by the near-field coupling between the RF/analog IC and logic IC is a severe problem in 3D mixed-signal systems. To reduce the vertical noise coupling, graphene is an appropriate material due to its inherent characteristics such as very low thickness, high flexibility, high mechanical strength, and EMI absorbing characteristic. Especially, the EMI absorbing characteristic is an important property as the shield to prevent the vertical noise coupling, as it reduces the re-coupling of the reflected EMI by the shield into other ICs. We measure the reduction of the vertical noise coupling by the mono-layer graphene shield in the 3D mixed-signal system composed of a low noise amplifier (LNA), an on-chip switching model DC-DC converter, and the mono-layer graphene in the frequency and time domain. Through the measurement results, we observed that the mono-layer graphene can maximally reduce the vertical noise coupling by -17 dB in the frequency domain. Additionally, the vertically coupled noise is reduced by 25% in the time domain measurement.

In this letter, we propose a vertical inductive bridge electromagnetic bandgap (VIB-EBG) structure for size reduction of a unit cell and the wideband suppression of simultaneous switching noise (SSN) in a multi-layer package. With the proposed vertical inductive bridge, the inductance of an EBG unit cell is effectivel increased within a compact unit cell size. Compared to the previous planar bridge EBG structure, the proposed VIB-EBG structure achieves an 86% enhancement of the fractional stopband bandwidth and a 58% reduction in unit cell size. The starting frequency of the first bandgap (fL) is significantly reduced from 4.0 to 1.7 GHz. Wideband SSN suppression with a size reduction was successfully verified by HFSS simulations and measurements.

In this paper, we designed the magnetically coupled resonators for wireless power transfer to mobile devices using field shaping technique. Power transfer to mobile devices is normally sensitive to variation of distance and alignment between transmitters and receivers. The magnetic field shaping technique, which is applied by On-line Electric Vehicle (OLEV) system, is considered to compensate the sensitivity, to reduce electromagnetic fields (EMF) around the receivers, and also to improve efficiency of power transfer [1]. We developed miniaturized coupled resonators to cover mobile devices, and enhanced coupling effect with modified formation of coupled resonators. Also, the coupled resonators are designed to receive power stably, less sensitive to variation of distance and alignment. We present measurement results with s-parameter value of the amount of power transferred.

In this paper, we propose a compact and wideband electromagnetic bandgap (EBG) structure using a defected ground structure (DGS) to significantly enhance the wideband suppression of power/ground noise coupling in multilayer packages and printed circuit boards. The proposed EBG structure is implemented simply by adding a rectangular-shaped DGS which is etched periodically onto the ground plane without changing any other geometrical parameter from a mushroom-type EBG structure. The DGS effects on the f $_L$ and f $_U$ are thoroughly analyzed using the dispersion characteristics. We experimentally verified that the proposed EBG structure achieved the wideband power/ground noise suppression (below −40 dB) between 2.5 and 16.2 GHz. In addition, we demonstrated the considerable reduction in f$_L$ from 3.4 to 2.5 GHz and a significant increase in f$_U$ from 9.1 to 16.2 GHz when compared with the mushroom-type EBG structure.

In this paper, we introduce a new decoupling capacitor stacked chip (DCSC) with discrete capacitors and through-silicon-vias (TSVs) that can overcome the limitations of the conventional decoupling capacitor solutions such as expensive on-chip NMOS capacitor and package-level discrete decoupling capacitor with narrow-band. The key idea of the proposed TSV-based DCSC is mounting the decoupling capacitors such as silicon-based NMOS capacitor and discrete capacitor on the backside of a chip and connecting the capacitors to the on-chip PDN through TSVs. Therefore, the TSV-based DCSC provides the lowest parasitic inductance (ESL: under several tens pH) through a short interconnections between the on-chip PDN and decoupling capacitors as well as the largest capacitance (up to several uF) by stacking the additional decoupling capacitors to 3D-IC systems.