Kyeounsoo Kim’s research while affiliated with Hanyang University and other places

This paper demonstrates the design of efficient asynchronous bundled-data pipelines for the matrix-vector multiplication core of discrete cosine transforms (DCTs). The architecture is optimized for both zero and small-valued data, typical in DCT applications, yielding both high average performance and low average power. The proposed bundled-data pipelines include novel data-dependent delay lines with integrated control circuitry to efficiently implement speculative completion sensing. The control circuits are based on a novel control-circuit template that simplifies the design of such nonlinear pipelines. Extensive post-layout back-end timing analysis was performed to gain confidence in the timing margins as well as to quantify performance and energy. Comparison with a synchronous counterpart suggests that our best asynchronous design yields 30% higher average throughput with negligible energy overhead.

This paper proposes an efficient asynchronous hardwired matrix-vector multiplier for the two-dimensional discrete cosine transform and inverse discrete cosine transform (DCT/IDCT). The design achieves low power and high performance by taking advantage of the typically large fraction of zero and small-valued data in DCT and IDCT applications. In particular, it skips multiplication by zero and dynamically activates/deactivates required bit-slices of fine-grain bit-partitioned adders using simplified, static-logic-based speculative completion sensing. The results extracted by both bit-level analysis and HSPICE simulations indicate significant improvements compared to traditional designs.

Introduction: The increasing demand for portable and wireless multimedia applications that rely on limited battery energy has made low power architectures and designs for these applications critical. Since real-time matrix transposition consumes a large fraction of the power in multi-dimensional image and signal processing, low-power matrix transposers are particularly important. When a digital circuit is implemented in CMOS, the largest energy is typically consumed by the dynamic power dissipation, which is expressed as (1/2)TC L V dd 2 f, where T is the circuit's transition activity, C L is the total capacitance, V dd and f are the supply voltage and the frequency of operation, respectively. The product TC L is referred to as the total switching capacitance of the circuit [1]. Various coding schemes, including bus-invert coding, re

This paper presents an efficient frame memory interface of MPEG-2 video encoder which is accomplished in not only reducing interface buffer size through efficient memory map organization and access timing schedules but also avoiding unnecessary small size buffers and simplifying their control circuits. In this design, 0.5 μm CMOS TLM (triple layer metal) standard cells are used as design libraries, and VHDL simulator and logic synthesis tools are used for hardware design and verification, and the hardware emulator that is a C-language model of the proposed architecture is exploited for various test vector generation and functional verification. The improved frame memory interface module takes about 58% less hardware area than the previous design (Kim et al. 1997), and results in reducing the total hardware area of the video encoder ASIC chip up to 24.3%. We also reduced the random memory accesses to save the power consumption caused by the transition of the system-level I/O buses

: This paper presents low-power asynchronous barrel shifters for variable length encoders and decoders useful in portable applications using multimedia standards. Our approach is to create multi-level asynchronous barrel shifters optimized for the skewed shift control statistics often found in these codecs. For common shifts, data passes through one level, whereas for rare shifts, data passes though multiple levels. We compare our optimized designs with the straight-forward asynchronous and synchronous designs. Both pre- and post-layout HSPICE simulation results indicate that, compared to their synchronous counterparts, our designs provide over a 40% savings in average energy consumption for a given average performance. 1 Introduction Asynchronous circuits sometimes can consume very low average energy for a given average performance partly because of their ability to adapt to variations in chip temperature and voltage supply level. To achieve this goal, however, the asynchronous circu...

In this paper, a VLSI architecture for DPCM Hybrid Coding Loop (DHCL), which consists of 2D-DCT, quantization, scan conversion, inverse quantization and 2D-IDCT, is presented. The architecture of the DHCL is designed to handle macroblock data within 1320 cycles and suitable for MPEG-2 video encoder accepting NTSC and PAL image formats. Only single 1-D DCT/IDCT is used for the design instead of 2-D DCT and IDCT to reduce the hardware size, and 3-bit serial distributed arithmetic architecture is adopted for 1-D IDCT to reduce the processing time in this architecture. As the result, the maximum utilization of hardware can be achieved, and power consumption can be minimized. The proposed designs can be operated on 80 MHz clock. The area is 50% smaller than the previous methods with 2D-DCT and IDCT. The experimental results show that the accuracy of DCT and IDCT meet the IEEE specification

This paper presents an area efficient VLSI architecture of transform coding module for MPEG-2 video encoder. This module consists of 2-D DCT and 2-D IDCT, Q and IQ, and zigzag and alternate scan conversion circuits. Hardware cost and performance of this module are mainly affected by the 2-D DCT and 2-D IDCT. In the proposed architecture, it is shown that a single 1-D DCT/IDCT could take the roles of the 2-D DCT and 2-D IDCT. It is capable of reusing a single 1-D DCT/IDCT four times. It is based on the row-column decomposition technique. It can be achieved through precise timing schedules. Intuitively, three 1-D DCT/IDCT and a matrix transposition memory could be saved as compared to the conventional architectures, which usually use two one-dimensional transforms and transposition memory. Even though there are some extra circuits due to timing controls and processing sequence schedules, this architecture takes about 24% and 50% respectively less area than the architectures published by Miyazaki et al. (1993) and by Matsiu et al. (1994). This design and implementation are applicable to the MPEG-2 video encoder accepting NTSC and PAL image formats in which the number of clocks to be allocated during a macro block period is 1320 for 54 MHz operating clock. To reduce its processing time, the proposed architecture uses a 3-bit serial distributed arithmetic method. As a result, this architecture can be characterized to maximize the utilization of the hardware resources, end can be used for encoders having a similar structure as the MPEC-2 video encoder. It also can be applied to the ASIC chips for multimedia services especially requiring low hardware complexity

This paper proposes a low-overhead MSB-controlled inversion coding technique to reduce the transition activity in a matrix transposer a commonly used component in 2-dimensional discrete cosine transform (DCT) and inverse DCT (IDCT) applications. A family of designs is identified in which this technique is applied to different bit slices of the matrix data and the optimal design within the family is determined using transition activity analysis driven by real image sequences. Our results suggest that the optimal design using MSB-controlled inversion coding yields power savings of 33% for DCT data and 46% for IDCT data. These results are remarkable since existing bus-invert coding techniques have high overheads and are only effective for system-level high-capacitive buses

This paper presents low-power asynchronous barrel shifters for variable length encoders and decoders useful in portable applications using multimedia standards. Our approach is to create multi-level asynchronous barrel shifters optimized for the skewed shift control statistics often found in these codecs. For common shifts, data passes through one level, whereas for rare shifts, data passes though multiple levels. We compare our optimized designs with the straight-forward asynchronous and synchronous designs. Both pre- and post-layout HSPICE simulation results indicate that, compared to their synchronous counterparts, our designs provide over a 40% savings in average energy consumption for a given average performance.