# Khaled M Elleithy's research while affiliated with King Fahd University of Petroleum and Minerals and other places

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## Publications (24)

In this paper two algorithms for register allocation are presented. The first algorithm is a simulated annealing algorithm. The core of the algorithm is the Metropolis procedure. The algorithm presented in the paper has a linear time asymptotic complexity. The second algorithm is a genetic algorithm. The algorithm has a linear time complexity.

In this paper a simulated annealing algorithm for register allocation is presented. The algorithm is based on the Metropolis procedure. The procedure accepts a new solution with less profit based on a probabilistic function. The objective of the heuristic is to color a graph representing the register allocation problem to maximize the profit functi...

In this paper a simulated annealing algorithm for register allocation is presented. The algorithm is based on the Metropolis procedure. The procedure accepts a new solution with less profit based on a probabilistic function. The objective of the heuristic is to color a graph representing the register allocation problem to maximize the profit functi...

In this paper two algorithms for register allocation are presented. The first algorithm is a simulated annealing algorithm. The core of the algorithm is the Metropolis procedure. The algorithm presented in the paper has a linear time asymptotic complexity. The second algorithm is a genetic algorithm. The algorithm has a linear time complexity.

In this paper, the verification strategy of PROVER environment is presented. The PROVER system (PROduction system for hardware VERification) is implemented using CLIPS (C Language Integrated Production System). PROVER is a rulebased framework for formal hardware verification. The environment supports verification at different levels of hardware spe...

Designing an optimal Residue Number System (RNS) processor in terms of area and speed depends on the choice of the system moduli. In this paper an optimal algorithm for choosing the system moduli is presented. The algorithm takes into consideration several constraints imposed by the problem definition. The problem is formalized as an integer progra...

Designing an optimal Residue Number System (RNS) processor in terms of area and speed depends on the choice of the system moduli. In this paper an optimal algorithm for choosing the system moduli is presented. The algorithm takes into consideration several constraints imposed by the problem definition. The problem is formalized as an integer progra...

Abstrcat The work reported in this paper is part of a silicon compiler that receives a parallel algorithm written in CIRCAL and produces a VLSI implementation. The implementation logic used is the asynchronous event logic. A generated netlist of event logic modules is used to produce the VLSI mask layout geometries for this circuit using the standa...

With the current advances in VLSI technology, traditional
algorithms for Residue Number System (RNS) based architectures should be
reevaluated to explore the new technology dimensions. In this brief, we
introduce A θ(log n) algorithm for large moduli multiplication
for RNS based architectures. A systolic array has been designed to
perform the modul...

In this paper a new approach for parallelism analysis and extraction of Digital Signa! Processing algorithms is introduced. The high level description of the input is given in CIRCAL. A dependency graph of the problem is constructed to check existence of cycles. Loops in the dependency graph are parallelized The approach is illustrated by an exampl...

In this paper a new approach for parallelism analysis and extraction of Digital Signa! Processing algorithms is introduced. The high level description of the input is given in CIRCAL. A dependency graph of the problem is constructed to check existence of cycles. Loops in the dependency graph are parallelized The approach is illustrated by an exampl...

In this tutorial paper the area of formal verification of DSP VLSI architectures is presented. The paper discuses the following topics: production systems, formal logic, the equational approach, and the signal flow graph approach. Each approache is explained using one or more of the current available systems.

In this paper, a rule-based framework for formal hardware verification is presented. The PROVER system (PROduction system for hardware VERification) is implemented using CLIPS (C Language Integrated Production System). The environment supports verification at different levels of hardware specification. The rule-based framework has been tested on th...

In this paper, a rule-based framework for formal hardware verification is presented. The PROVER system (PROduction system for hardware VERification) is implemented using CLIPS (C Language Integrated Production System). The environment supports verification at different levels of hardware specification. The rule-based framework has been tested on th...

In this paper a new formal hardware verification approach for Digital Signal Processing Architectures based on a production system environment is introduced. The PROPER system (2?ROduction system for hardware WRification) is implemented using CLIPS (C Language Integrated Production S'tstem). A cell library of diferent hardware components has been i...

In this paper a formal design methodorogy is used to design a Residue Number System (RNS) processor. An optimal architecture for the residue decoding pro-cess is obtained through this design approach. The architecture is modular, con-sists of simple cells, and is general for any set of moduli. -1. Introduction A novel approach for synthesizing digi...

In this paper, we introduce a formal approach for synthesis of array architectures. Four different fovms are used t o express the input algorithm: simultaneous recursion, recursion with respect t o dsferent vari-ables, fixed nesting and variable nesting. Four different architectures for the same algorithm are obtained. As an example, a matrix-matri...

In this paper, we introduce a formal approach for synthesis of array architectures. Four different fovms are used t o express the input algorithm: simultaneous recursion, recursion with respect t o dsferent vari-ables, fixed nesting and variable nesting. Four different architectures for the same algorithm are obtained. As an example, a matrix-matri...

Absfrad -A O(l) algorithm for large modulo addition for residue number system (RNS) based archictectures is proposed. The addition is done in a fixed number of stages which does not depend on the size of the modulus. The proposed modulo adder is much faster than the previous adders and more area efficient. The implementation of the adder is modular...

A θ(log n ) algorithm for large moduli multiplication for residue-number-system (RNS)-based architectures is proposed. The modulo multiplier is much faster than previously proposed multipliers, and more area efficient. The implementation of the multiplier is modular and is based on simple cells, which leads to efficient VLSI realization. A VLSI imp...

Decoding in Residue Number System (RNS) based architectures can be a bottleneck. A high speed and flexible modulo decoder is an essential computational element to maintain the advantages of RNS. In this paper, a fast and flexible modulo decoder, based on the Chinese Remainder Theorem (CRT), is presented. It decodes a set of residues into its equiva...

A #(fog n) algorithm for large moduli multiplication for Residue Number System(FtNS) based architectures is proposed. The proposed modulo multiplier is much faster than previously proposed multipliers and more area efficient. The implementation of the multiplier is modular and is based on simple cells which leads to efficient VLSI realization. A VL...

In this paper, an implementation of a f-t and flexible rscidue decoder based on Chinese Remainder Theorem, or CRT, is propolrad to decode a set of nsiduea to ita equivalent reprasentation in weighted binary number system. This decoder is flexible since the decoded data can be selected to be either unsigned magnitude or 2's comple-ment binary number...

In this paper, an implementation of a f-t and flexible rscidue decoder based on Chinese Remainder Theorem, or CRT, is propolrad to decode a set of nsiduea to ita equivalent reprasentation in weighted binary number system. This decoder is flexible since the decoded data can be selected to be either unsigned magnitude or 2's comple-ment binary number...

## Citations

... In [14] and [16] a generic structure for modular compressing of four inputs to two outputs is presented. This structure computes the modular reduction in five steps as depicted in Figure 1(a). ...