Kevin Tshun Chuan Chai’s research while affiliated with Agency for Science, Technology and Research (A*STAR) and other places

This article presents a novel dual 7T static random-access memory (SRAM)-based compute-in-memory (CIM) macro for processing quantized neural networks. The proposed SRAM-based CIM macro decouples read/write operations and employs a zero-input/weight skipping scheme. A 65nm test chip with $528\times 128$ integrated dual 7T bitcells demonstrated reconfigurable precision multiply and accumulate operations with 384 $\times$ binary inputs (0/1) and $384\times 128$ programmable multi-bit weights (3/7/15-levels). Each column comprises 384 $\times$ bitcells for a dot product, 48 $\times$ bitcells for offset calibration, and 96 $\times$ bitcells for binary-searching analog-to-digital conversion. The analog-to-digital converter (ADC) converts a voltage difference between two read bitlines (i.e., an analog dot-product result) to a 1-6b digital output code using binary searching in 1-6 conversion cycles using replica bitcells. The test chip with 66Kb embedded dual SRAM bitcells was evaluated for processing neural networks, including the MNIST image classifications using a multi-layer perceptron (MLP) model with its layer configuration of 784-256-256-256-10 The measured classification accuracies are 97.62%, 97.65%, and 97.72% for the 3, 7, and 15 level weights, respectively. The accuracy degradations are only 0.58 to 0.74% off the baseline with software simulations. For the VGG6 model using the CIFAR-10 image dataset, the accuracies are 88.59%, 88.21%, and 89.07% for the 3, 7, and 15 level weights, with degradations of only 0.6 to 1.32% off the software baseline. The measured energy efficiencies are 258.5, 67.9, and 23.9 TOPS/W for the 3, 7, and 15 level weights, respectively, measured at 0.45/0.8V supplies.

This brief presents a low-power and low-noise K-band (18-21.2GHz) analog beamforming receiver (BFIC-Rx) IC for Satcom on the Move (SOTM) applications. The BFIC-Rx employs a 2-stage cascode LNA, a modified Gilbert-cell type dB-linear VGA and a passive phase shifter (PS) in the signal chain for low cascaded noise figure (NF) and low power consumption. The cascode LNA has low NF and a high gain of 24dB for RF input isolation to the subsequent stages. The VGA has a 15dB dB-linear gain, controllable in 0.5dB fine steps, and a 180° phase shift feature. The passive PS has 5-bit control plus 2 bits for calibration and together with VGA’s 180°, achieves a total phase shift of 360°. The BFIC-Rx achieves a state-of-art NF of 2.32dB, a total signal gain of 31dB, IP1dB of −35.8 dBm, phase, and amplitude error of 1.1° and < 0.5dB respectively while consuming only 35mW from a 1.8V supply ${\text{@}}~19.5$ GHz. The BFIC-Rx was fabricated on a 130nm SiGe process and occupies a core area of $1.5 \times 0.8$ mm2. The low NF, high signal gain, and low power are critical parameters to enable large-scale efficient phased arrays for SOTM applications in the toughest conditions.

This work presents a hardware accelerator realizing true time-domain wavefront computing in a massive parallel two-dimensional (2-D) processing element (PE) array. The proposed 2-D time-domain PE array is designed for multiple applications based on its scalable and reconfigurable architecture. The shortest path problem (a classical problem in graph theory) is one of the critical problems to solve using the proposed accelerator. Unlike the A ${}^\ast$ search algorithm, a heuristic method widely used in shortest path searching problems, the proposed accelerator requires only the propagation of rising-edge signals through the PE array without calculating or estimating the distances from the start to the goal. Hence, a single execution of the proposed time-domain wavefront computing provides all the optimal paths from a start point to an arbitrary goal. Besides the King’s graph model used for solving the shortest path searching, the PE array is reconfigured to a simpler lattice graph model and solves other problems, such as maze solving we used in this article as a benchmark. In addition, we used the proposed accelerator to demonstrate a scientific simulation. The propagation of circular or planar wavefronts was simulated using single or multiple start points using King’s graph configuration. A 1 $\times$ 1 mm $^{2}$ test chip with a 32 $\times$ 32 reconfigurable time-domain PE array is fabricated using a 65-nm process. For a 2-D map with 32 $\times$ 32 vertices, the proposed PE array consumes 776 pJ per task and achieves 1.6 G edges/second search rate using 1.2-/1.0-V core supply voltages.