Kazuma Sakatoh’s research while affiliated with Chuo University and other places

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Publications (1)


Circuit techniques to enhance linearity and intrinsic gain to realize a 1.2 V, 200 MHz, +10.3 dBm IIP3 and 7th-Order LPF in a 65 nm CMOS
  • Article

June 2013

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8 Reads

IEICE Transactions on Electronics

Yasuhiro Sugimoto

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Kazuma Sakatoh

Circuit techniques to enhance the linearity of input-voltage-to-current (V/I) conversion and to increase the output impedance of a current source by compensating for the low intrinsic gain of a transistor were introduced to realize a high-frequency operational transconductance amplifier (OTA) for a low supply voltage using sub-100-nm CMOS processes. Applying these techniques, a MOS 7th-order Gm-C linear-phase low-pass filter (LPF) was realized using a 65 nm CMOS process. A simplified biquad LPF that can serve as a component of a 7th-order LPF was newly developed by replacing OTAs with resistors. As a result, the -3 dB frequency bandwidth, group delay ripple, 3rd-order distortion, and 3rd-order input intercept point (IIP3) were 200 MHz, 2.2%, ≤ -55 dB with a 100 MHz input, and +10.3 dBm, respectively, all with a ±0.1 Vp-p input signal at each input terminal in the pseudodifferential configuration. The LPF including an output buffer dissipated 60 mW in the case of a 1.2 V supply. Wide spurious-free dynamic range (SFDR) characteristics were confirmed up to high frequencies. Copyright © 2013 The Institute of Electronics, Information and Communication Engineers.