Joseph Basile’s research while affiliated with Intel and other places

We report on radiation-induced soft error rate (SER) improvements in the 14-nm second generation ${hbox{high-}} {rm k} + {hbox{metal}}$ gate bulk tri-gate technology. Upset rates of memory cells, sequential elements, and combinational logic were investigated for terrestrial radiation environments, including thermal and high-energy neutrons, high-energy protons, and alpha-particles. SER improvements up to $sim!! 23times$ with respect to devices manufactured in a 32-nm planar technology are observed. The improvements are particularly pronounced in logic devices, where aggressive fin depopulation combined with scaling of relevant fin parameters results in a $sim!! 8times$ reduction of upset rates relative to the first-generation tri-gate technology.

We report on measured radiation-induced soft error rates (SER) of memory and logic devices built in a 22 nm high-k metal gate bulk Tri-Gate technology. Our results demonstrate excellent single event upset (SEU) scaling benefits of tri-gate devices. For cosmic radiation, SEU SER reduction levels of the order of are observed relative to 32 nm planar devices, while for alpha-particles, the measured SEU SER benefit is in excess of . Similar improvements are observed for Tri-Gate combinational logic and memory array multi-cell upset (MCU) rates. Reduced SER (RSER) device SER performances (relative to standard, non -RSER devices) are on par or better than that of tested 32 nm planar devices. Finally, a novel, efficient SER reduction design called RTS is introduced.