Jingjing Liu’s research while affiliated with Sun Yat-Sen University and other places

This paper presents a subthreshold CMOS voltage reference (VR) that utilizes self‐biased circuits. This voltage reference includes temperature compensation circuits to expand its operating temperature range and reduce its temperature coefficient. The proposed CMOS voltage reference is designed using a standard 0.18‐μm CMOS process and has a small area of only 0.005 mm ² . Post‐layout simulation results demonstrate that the power consumption of the circuit at room temperature (25°C) is only 1.65 nW at a power supply voltage of 1 V. In this case, the voltage reference output is 316.56 mV, with an average temperature coefficient (TC) of 11.14 ppm/°C in a wide temperature range from −40°C to 140°C. Furthermore, the line sensitivity (LS) of the circuit is 0.024%/V, and the power supply rejection ratio (PSRR) of the circuit is −86.5 dB at 10 Hz. In summary, the subthreshold CMOS voltage reference structure proposed in this paper demonstrates excellent performance characteristics, such as low power consumption, a small area, and high‐temperature stability. These features make it a promising candidate for voltage reference for low‐power applications with significant changes in environmental temperature.

Fluorescent optical fiber temperature sensors require accurate online temperature monitoring in hazardous environments with strong electromagnetic fields, high voltages, flammability, or explosiveness. This imposes stringent requirements on the temperature coefficient stability of the bandgap reference (BGR) circuit. To address these challenges, this paper proposes a high‐order curvature compensation bandgap reference (HCC_BGR) circuit fabricated using a 0.18‐μm bipolar‐CMOS‐DMOS (BCD) process. A traditional first‐order bandgap reference (TRA_BGR) circuit is also fabricated for comparison. Experimental results demonstrate that the proposed HCC_BGR circuit generates a stable 1.22‐V reference voltage with a low‐temperature coefficient of 5.56 ppm/°C from −20°C to 85°C. Compared to the TRA_BGR circuit, the HCC_BGR reduces the temperature coefficient by 3.07 times. Furthermore, the low‐dropout regulator (LDO) using the proposed HCC_BGR exhibits excellent line sensitivity of 1.52%/V from 3.4 to 5 V.

Enhancing the photoelectric conversion efficiency of on-chip solar cells is important for the realization of self-powered smart microsensors. The surface electrode models for the on-chip solar cell based on CMOS process is constructed. It is verified by simulations and measurements that square ring electrode (RE) and center electrode (CE) don’t cause significant differences in the internal resistance of solar cells. Adopting the CEs instead of the REs can significantly reduce the shadowing effect of surface electrodes. To solve the problem of light blockage caused by the metal interconnections in the segmented solar cells, highly doped regions are used to replace some of the metal interconnections. A 0.01mm2 segmented triple-well on-chip solar cells with the CEs and highly doped region as interconnection is fabricated using a standard 0.18μm CMOS process. Measurement results show a 25.79% photoelectric conversion efficiency under solar simulator illuminations and has a 17.49% improvement compared to the conventional design. Utilizing the proposed solar cells, an on-chip energy harvesting power source has been realized, achieving a maximum conversion efficiency of 10.20% from incident solar power to voltage output power. Despite variations in illumination and load, this power source is able to maintain a relatively stable output voltage of 1V.

Fluorescence optical fiber temperature sensors have found widespread use in harsh environments with electromagnetic interference, high voltages, flammability, and combustibility due to their excellent insulating properties. However, conventional fluorescence detection systems are constructed from discrete photodiodes and other front-end circuit chips, which cause bulky size, inferior detection efficiency, and degraded signal-to-noise performance. To address these issues, an integrated optical front-end circuit for fluorescence detection was proposed. The front-end circuit monolithically integrated a ring-gate-isolated photodiode (RGI-PD) device, a transimpedance amplifier (TIA), and a bandgap reference (BGR) circuit. The RGI-PD enabled the detection of the fluorescence afterglow signals, while the TIA circuit converted the photocurrent generated by the RGI-PD into a measurable photovoltage output. The RGI-PD utilized a P-well guard ring structure to prevent edge breakdown by isolating the avalanche region from the shallow trench. The dummy ring-gate created an inverted pyramid hole profile, focusing the electric field on the planar junction to enhance photodetection, which reduced trapping effects and dark counts. The proposed front-end circuit was fabricated using a standard $0.18~\mu \text{m}$ bipolar CMOS DMOS (BCD) process. The measurement results demonstrated that the avalanche breakdown voltage (BV) of the RGI-PD was 13.05 V. The front-end circuit achieved a responsivity of 17.29 A/W at 500 nm wavelength, under a 13.88 V reverse bias voltage applied on the RGI-PD. Moreover, the front-end’s dark voltage measured 0.908 V, with an optimal temperature coefficient (TC) of 41.01 ppm/°C within the temperature range of −40 °C to 85 °C. The proposed front-end circuit was suitable for fluorescence fiber temperature sensing applications.

Image sensors with energy harvesting capabilities aid in the development of self-powered IoT nodes. By achieving simultaneous energy harvesting and imaging, these image sensors make it possible to eliminate batteries and directly achieve self-powered operation. The paper proposes a 1V wide swing image sensor with simultaneous energy harvesting and imaging modes. The proposed pixel utilizes a vertical N+/P-well/DNW/P-sub structures as the photodiode based on a standard 180nm CMOS mixed-signal process. The N+/P-well is used for imaging, while the P-well/DNW and DNW/P-sub are used for energy harvesting with P-well and P-sub shorted together. Moreover, a traditional 4T pixel has been improved by using CMOS pairs as the switches and zero-threshold NMOS as the source follower. The rail-to-rail pixel output swing can be achieved. An image sensor with simultaneous energy harvesting and imaging modes, which consists of a 32×32 pixel array, a controller and a dual-channel PWM quantizer, has been designed and fabricated. Measurement results show that the average power consumption of the image sensor is approximately 899.6nW with 25fps at 3klx. The proposed image sensor has a DR of 47.3 dB under 1V supply. The measured power generated by energy harvesting while maintaining imaging functionality is 194pW/lx/mm².

Physiological information provided by bio-potential signals is essential and pivotal for biomedical sensors. As the first stage in the signal chain of the sensor, impedance matching of the analog front-end (AFE) is critical for determining signal integrity. AFEs require high input impedance to minimize the effects of electrode impedance mismatch. A significant problem is that the input impedance is affected by parasitic capacitances from the integrated circuit (IC) package, electrode cables, and internal chips. This paper aims to summarize the development of AFE impedance boosting techniques for bio-potential monitoring. The scope of this work includes a review of common architectures for instrumentation amplifiers (IA), mechanisms for input impedance reduction, and a comparison of impedance boosting factors (IBF) employed to evaluate the efficiency of impedance enhancement. Techniques schemes for boosting input impedance in architectures are then surveyed and the contributions and drawbacks of these techniques are discussed. Finally, the state-of-the-art designs of AFE are compared and summarized, along with an analysis of the trend toward enhanced input impedance in bio-electrical signal acquisition. These provide useful references for AFE designers.