January 2009
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16 Reads
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Publications (28)
May 2008
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6 Reads
May 2008
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8 Reads
May 2008
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3 Reads
May 2008
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11 Reads
Introduction Description of the Cryptographic Algorithms Implementation Proposal Expermental Analysis Conclusions References
January 2007
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22 Reads
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14 Citations
In this paper we show and analyse the different alternatives used to implement, until now, artificial neural networks in FPGAs. At the moment, this is a very active research field, and still, there is a long way to travel. In this work, we focus on important aspects like: the neuron's multiplier and activation function implementation, the storage and representation of the implicated data, the most habitual improvements and simplifications, the reconfigurable hardware systems used to implement artificial neural networks,... Ending this paper with the conclusions obtained from this analysis work. Among them, it is important to highlight that the use of FPGAs to implement ANN is not only feasible, but also presents a hopeful future.
June 2006
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23 Reads
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3 Citations
Nowadays, the information security has achieved a great importance, both when information is sent through a non-secure network (as the Internet) and when data are stored in massive storage devices. The cryptographic algorithms are used in order to guarantee the security of data sent or stored. A lot of research is being done in order to try to improve the performance of the current cryptographic algorithms, including the use of FPGAs. In this work, we present a detailed research of the IDEA cryptographic algorithm implementation in VirtexE and Virtex2 FPGAs. Six different hardware implementations are presented, which are compared with each other and with the algorithm software implementation. In conclusion, the implementation of the IDEA algorithm using FPGAs offers advantages over software implementation, obtaining a performance 28 times better than the software version
January 2005
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11 Reads
Studies in Fuzziness and Soft Computing
In this chapter a methodology for circuit design using Multi-FPGA Systems has been presented. We have used evolutionary computation for all the steps of the process. Firstly, an Hybrid compact genetic algorithm was applied on achieving partitioning and placement for inter-FPGA systems and, for the Intra-FPGA tasks Genetic programming was used. This method can be applied for different boards and solves the whole design flow process.
January 2005
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24 Reads
In this work we present a parallel technique to optimize time series modelling in order to ob- tain high precision predictions. Also, this technique could be very useful when the high precision mathematical modelling of dynamic complex systems is required. We employ System Identification algorithms, and use recursive least squares processing and ARMAX modelling. After explaining the proposed heuristic (a set of parallel processing units that performs an adaptive algorithm) and the tuning of its parameters, we show the results we have found for several benchmarks. Thus, we demonstrate how the result precision improves.
September 2004
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21 Reads
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5 Citations
Microprocessors and Microsystems
In this paper, we present a methodology for Multi-FPGA systems (MFS) design. MFSs are used for a great variety of applications, including dynamically re-configurable hardware applications, digital circuit emulation, and numerical computation. There are a great variety of boards for MFS implementation. We have employed a set of techniques based on evolutionary algorithms, and we show that they are capable of solving all of the design tasks (partitioning placement and routing). Firstly a hybrid compact genetic algorithm solves the partitioning problem and then genetic programming is used to obtain a solution for the two other tasks.
Citations (13)
... A processor can compute the fitness of each solu-1 Here, robustness of parallel algorithms refers to potential improvements on result quality (Cantu-Paz, 2000), having a natural affinity to alleviate the bloat phenomenon Ruciński et al. (2010);Fernández et al. (2002); Trujillo et al. (2016); Kucukyilmaz and Kiziloz (2018), and having a better scalability potential Liu and Wang (2015); Dokeroglu and Cosar (2016). Especially when using evolutionary approaches, several studies indicate that parallel frameworks maintain population diversity better than non-parallel counterparts, allowing better exploration for the framework and hence improvements in terms of result quality Andre and Koza (1996);Fernández et al. (2000Fernández et al. ( , 2013; Kucukyilmaz and Kiziloz (2018). tion. ...
Reference:
Hyper-heuristics: A survey and taxonomy
- Citing Conference Paper
January 2000
Lecture Notes in Computer Science
... Otros cursos incorporan a los dispositivos FPGA dentro de su programas académicos. Por ejemplo, [18] hace uso de sesiones prácticas de laboratorio para el diseño de Unidades Aritmético Lógicas, unidades de memoria y unidades de control a través de Handel-C. Así también, contempla sesiones para la enseñanza de la paquetería ISE de Xilinx y el uso de Visual C++. ...
- Citing Article
... Any pair of states are compatible if they share the same output symbol and 70 next state. Moreover, a compatible class C i is a set of states where every pair of states is compatible (Sánchez et al., 1995). It is said that a compatible class covers another compatible class, if it contains all pairs of compatible states of the covered class. ...
- Citing Article
July 1995
Microelectronics Journal
... N DIGITAL logic design, spectral techniques have been I used for more than 30 years. They have been applied to Boolean function classification [9], 1221, 1231, [36], 1371, disjoint decomposition 1231, [50]- [52], [54], parallel and serial linear decomposition [lo], 1221-1251, [51], [52], 1541, spectral translation synthesis (extraction of linear pre-and post-filters) 1101, [ [47] can be solved very easily in the spectral domain because complementing the Boolean function corresponds to changing the sign of every spectral coefficient [22], [23]. Tautology of a Boolean function can be verified by calculating a certain coefficient (DC coefficient). ...
- Citing Article
March 1989
International Journal of Electronics
... En relación con la electrónica evolutiva nos encontramos también con el campo del hardware evolutivo (EHW, por sus siglas en inglés), que se caracteriza por realizar la evaluación de los circuitos candidatos en el propio hardware, en cuyo caso la evaluación se denomina evaluación intrínseca. En este ámbito es muy habitual el uso de sistemas basados en una matriz de puertas lógicas programables (FPGA, por sus siglas en inglés) o en una matriz de componentes analógicos programables (FPAA, por sus siglas en inglés), que son unos tipos de CI que permiten su programación con la configuración del circuito candidato a evaluar (Higuchi et al., 1996;Hidalgo et al., 2003). ...
- Citing Conference Paper
- Full-text available
June 2003
Lecture Notes in Computer Science
... Abi įmonės gamina analogiškus produktus ir teikia programavimo bei plėtros aplinkas. LPLM dėl savo ypatingo lankstumo taip pat naudojamas DNT algoritmams vykdyti (Sahin, Beceriki, Yazici 2006;Muthuramalingam, Himavathi, Srinivasan 2007;Granado et al. 2006). Pastaruoju metu atlikti tyrimai rodo, kad LPLM gali prilygti kai kurioms GPĮ pagal našumą ir naudoja 10-20 kartų mažiau galios bei gerai tinka nedideliems SDNT vykdyti (Ovtcharov et al. 2015;Kayaer, Tavsanoglu 2008;Zhang et al. 2015;Farabet et al. 2011). ...
- Citing Conference Paper
January 2007
... Performance analysis of encryption algorithms for security [1], A Comparative and Analytical Study on Symmetric [2], Dessign of new security algorithm [3], Comparative Analysis of NPN Algorithm & DES [4], Proposed Symmetric Key Cryptography Algorithm [5], Comprehensive Study of Symmetric Key and Asymmetric Key Encryption Algorithms [6], Performance Evaluation of Cryptographic Algorithms: DES and AES [7], DES and AES Performance Evaluation [8], Differential fault analysis against AES-192 and AES-256 with minimal faults [9] ,Implementing the IDEA Cryptographic Algorithm in Virtex-E and Virtex-II FPGAs [10], User Defined Encryption Procedure for IDEA Algorithm [11], Performance evaluation for CAST and RC5 encryption algorithms [12], Selection of parameter 'r' in RC5 algorithm on the basis of prime number [13] , Design and implementation of algorithm for des cryptanalysis [14], A-RSA: Augmented RSA [15], High speed implementation of RSA algorithm with modified keys exchange [16]. ...
- Citing Conference Paper
June 2006
... However, natural biological evolution is also about 'hardware' since the end process is a physical biological system. There have been several applications of evolutionary computing methodologies to new manufacturing techniques, such as fabrication of advanced FPGA (Fernández et al., 2004) and topology optimized geometries (Chen and Hwang, 2009), among many more as presented in section 3.3. Nevertheless, most evolutionary methodologies are applied to the systems engineering side of a product design such as form assessment (Shieh et al., 2018), structure optimization (Ma et al., 2020), and control development systems engineering (Yan et al., 2011). ...
- Citing Article
September 2004
Microprocessors and Microsystems
... Traditionally, controlling complexity in GP means controlling the size of the representation of the evolved models (bloat-control), such as by limiting the number of nodes, encapsulated sub-trees and layers. Bloat-control can ease the challenge associated with the unwanted growth in the structures of GP individuals that can exhaust computational resources and severely stifle the search for solutions [1,[146][147][148][149][150][151]. However, bloat-control ignores the underlying functional or computational complexity of the solutions. ...
- Citing Conference Paper
December 2002
... LAGEP achieved comparable results to single population GP in much less time. The GP was used with several isolated subpopulations, where the individuals among the several populations were not allowed to communicate [55]. This methodology was referred to as isolated multipopulation genetic programming (IMGP). ...
- Citing Conference Paper
February 2000