J.K. Wolf's research while affiliated with University of California, San Diego and other places

... Constrained coding is a method of eliminating error-prone sequences in data recording and communication systems, by encoding arbitrary user data sequences into sequences that respect a constraint (see, for example, [1] or [2]). In this work, we consider the problem of designing explicit constrained binary codes that achieve good rates of transmission over a noisy binary memoryless symmetric (BMS) channel. ...

... NAND flash memory exhibits limited endurance, which is typically specified by the maximum number of program-erase operations (or PE cycles) allowed on a memory block. The number of PE cycles may impact the nominal page program time, t prog , and stressed pages with a high number of PE cycles may take more time to program [29][30][31]. Hence, an implementation of EXPRESS needs to consider the number of PE cycles. Figure 12a shows the cumulative distribution of the nominal page program time for SLC pages in a fresh flash memory block, and in a memory block that has been exposed to 10,000 PE cycles. ...

... The eIRA codes can be designed to have bit-error-rate floors below and codeword-error-rate floors below [20], [21]. The matrices have a semirandom format (1) where is a sparse random matrix containing no weight-two columns and is a full-rank matrix given by (2) Note that, with in the above form, encoding may be performed directly from the matrix. That is, one may solve for the parity bits recursively from . ...

... In this section, frame error rate performance of irregular turbo codes over the BEC is shown. Although the analysis so far is based on the BCJR algorithm that supposes soft information exchange, it was shown in [8] that a hard-input hard-output (HIHO) decoding algorithm (namely the Viterbi algorithm [27]) for convolutional codes is optimal in terms of bit error probability over the BEC. For this reason, we will use a HIHO decoding algorithm for irregular turbo codes inspired by the algorithm in [28] for LDPC codes, in that it propagates in the trellis of the turbo code by removing transitions in the same way edges are removed in a bipartite graph under message-passing decoding [29]. ...

... The procedure defined above can be regarded as a function from a set of 1D data sequences to 2D patterns. The function can also be regarded as a variant of bit stuffing algorithm in [12], [13], [14]. Hence the procedure can be used in calculating lower bounds of the capacity of a given constrain [15]. ...

... capacity signal-to-noise-ratio (SNR) limit [61], [62], [70], [145]. 7 In the past two decades, many researchers have tried to develop effective algorithms to calculate the SIR of MR systems [64]- [67], [70], [126], [145]. To be specific, the SIR of OD-ISI channels has first been investigated in [61], [70], [145], which has been subsequently generalized to SIR of TD-ISI channels [64]- [67], [126]. ...

... A dynamic programming method [18] is studied to write precompensate the NLTS and partial erasure in a longitudinal recording channel. Later a twolevel precompensation scheme [19] is proposed to apply precompensation according to the transition pattern in the two preceding bit positions for the conventional perpendicular recording channel. ...

... 1) There are many papers in the literature discussing TD constrained coding. Bounds on the capacity of TD RLL codes were discussed in [47] and [48]. Explicit coding techniques to stuff bits into a TD grid such that certain RLL constraints are satisfied in both directions were presented in [25] and [26]. ...

... Techniques to reduce or tolerate cell wear have been examined for flash and emerging non-volatile memory devices. In general, these techniques fall into three categories depending on if they reduce wear by (1) throttling writes to a device (e.g., [179]), by (2) converting data to a representation that does not cause as much wear (e.g., [79]), or by (3) wear-leveling writes to a device (e.g., [29,139,142,254,317,318,253] Techniques to reduce or tolerate cell wear per unit time have been examined extensively for storage technologies, most notably non-volatile storage and memory devices [29,139,142,254,317,318,253]. ...

... If a complete SP is erased, all check nodes that have connections to this SP have at least two erased connections and hence, the erased variable nodes of that SP are not recoverable. This situation has been studied in [14], where the authors additionally provide protograph constructions that avoid this situation and additionally maximize the correctable burst length given some structural constraints of the code. To correct bursts encompassing an SP, the authors in [15] apply interleaving (therein denoted band splitting) to a protograph-based SC-LDPC code. ...