J.H. Lee’s research while affiliated with Kyungpook National University and other places

... LEL can present as unilateral or bilateral following surgical treatment. Most often LEL presents unilaterally; however, approximately 20% of LEL is bilateral [13,43,44,94,99]. Our difference in leg circumference measures may have missed bilateral LEL and partially account for the higher prevalence identified by the GCLQ. ...

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Lymphedema self-assessment among endometrial cancer survivors

... Such stray magnetic fields could originate from the RL and synthetic antiferromagnet (SAF) layers in the MTJ structure [10]. Other modes for increased WER could be back-hopping [11], process variations, inhomogeneity of material parameters [12], etc. Our recent study employing micromagnetic simulations showed that poorly designed SAF and RL layers could cause WER ballooning in MTJ devices with relatively larger diameters [10]. ...

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Write error ballooning due to anisotropy variation within the free layer in perpendicular magnetic tunnel junctions

... An alternative design involves a fully vertical arrangement 131 , where the capacitor is aligned with the channel to enhance device performance. Both of these 3D integration methods share a similar framework and operational principles to those used in VC-FeNAND technology, which has been shown to deliver high-density storage solutions.The vertical stacking 3D 1T-1C FeRAM architecture utilizes monolithic stacking to achieve high memory density and performance, similar to the 3D DRAM132,133 . For each layer, a horizontal gate-all-around (GAA) access transistor and horizontal MFM or metalferroelectric-semiconductor (MFS) capacitor can be adopted. ...

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A Full Spectrum of 3D Ferroelectric Memory Architectures Shaped by Polarization Sensing

... In the miniaturization process, the channel size is cut down, which decreases the distance between the source and drain and effectively reduces the performance of the device by encountering the SCEs. To avoid these issues, spacers are introduced between the two potential terminals of the device, which allow downscaling of the device to a sub-10 nm regime [5,6,[20][21][22][23]. Sreenivasulu et al [6], further enhanced the device performance by combining the High-K spacer to minimize the series resistance of the substrate and enhance the drain current. ...

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Design of high-K dielectric HSS-DMG Junctionless FinFET using hetero GOS for nanoscale application

... At IEDM 2022, the 28 nm MRAM was also presented as a standalone technology with operating voltages of 1.8/3.3 V, operating temperatures of −40 to 85℃, 40/160 ns read/write speed, a switching endurance of 10 14 cycles, although at −25℃, and 10 years data retention at 89℃. [60] In the same paper, a further improvement to an embedded 14 nm node was presented (−40 to 105℃ operating temperature, 15/50 ns read/write speed, 12 pJ/bit write energy), and the 14 nm automotive technology was presented at VLSI 2024 with a switching endurance of 10 12 cycles, 100 ns write speed, and 10 years data retention at 150℃. [61] Also at VLSI 2024, in collaboration with IBM, <5 ns switching STT-MRAM was presented with high H c > 8 KOe and high E b > 80 k B T. [27] Samsung 8 nm MRAM is planned by 2026 and 5 nm by 2027. ...

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Progress of emerging non-volatile memory technologies in industry

... Bit error rate of array. (a) Pre-optimization; (b) Pro-optimization.[88]. ...

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自旋轨道力矩磁性随机存储器制造工艺研究

... These remarkable performances have been achieved through downscaling of device feature size, an optimized fabrication process, and optimized InGaAs channel materials for excellent transport properties. In addition, InGaAs channel MOSFETs have shown outstanding logic performance on various substrates, such as InP and flexible substrates, with extensive efforts to enhance their capability in new device structures, S/D Ohmic contacts, and optimization of the gate stack [4][5][6][7]. Meanwhile, large-size and cheaper-cost substrates will be essential for largevolume manufacturing from a mass production point of view, but an InP substrate is more expensive than a GaAs substrate, and the size to date is limited to 6 inches. ...

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Fabrication and Characterization of In0.53Ga0.47As/InAs/In0.53Ga0.47As Composite Channel Metamorphic HEMTs (mHEMTs) on a GaAs Substrate

... Samsung demonstrated a denser 28 nm node eMRAM (13.9 Mb mm -2 ) for use as a frame-buffer memory in CMOS image sensor applications, a very different application to eNVM, with 10 10 write endurance over the operating range −20 °C to 85 °C, and a fast write of 50 ns relative to 200 ns for eNVM for standard eFlash replacement. The trade-off is that only 1 s retention at 85 °C is needed for this application 30 . Sony has also demonstrated a 40 nm node eMRAM for use as a buffer memory for CMOS image sensor applications 31 . ...

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Spin-transfer torque magnetoresistive random access memory technology status and future directions

... is at the heart of MRAM technology [3,4], and has proven particularly effective in tunnel magnetoresistive devices and circuits [5,6]. Spin transfer torque (STT)-MRAM devices with a CoFeB/MgO/CoFeB heterostructure provide high thermal stability and a low damping constant [7]. ...

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Interface Imperfection Effects on Spin Transfer Torque Switching: an Atomistic Approach

... In-memory computing (IMC) and near-memory computing (NMC) with an embedded memory are promising solutions to address these issues [1], [2], [3]. Recently, several candidates have been proposed for embedded memory applications such as eDRAM [4], RRAM [5], and MRAM [6]. Although memory elements are placed in a back-end-of-line (BEOL) layer in a conventional embedded memory architecture, access transistors are located in a front-end-of-line (FEOL) layer. ...

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High-Field Transport and Statistical Variability of Nanosheet Oxide Semiconductor FETs With Channel Length Scaling