J. Sleight’s research while affiliated with IBM Research - Thomas J. Watson Research Center and other places

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Publications (55)


Performance Stabilization of High-Coherence Superconducting Qubits
  • Preprint

March 2025

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3 Reads

Andrew Dane

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Karthik Balakrishnan

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Brent Wacaser

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[...]

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Jeffrey Sleight

Superconducting qubits have been used in the most advanced demonstrations of quantum information processing, and they can be manufactured at-scale using proven semiconductor techniques. This makes them one of the leading technologies in the race to demonstrate useful quantum computers. Since their initial demonstration, advances in design, fabrication, and materials have extended the timescales over which fragile quantum information can be stored and manipulated on superconducting qubits. Ubiquitous atomic-scale material defects have been identified as a primary cause of qubit energy-loss and decoherence. Here we study transmon qubits that exhibit energy relaxation times exceeding 2.5 ms. Even at these long timescales, our qubit energy loss is dominated by two level systems (TLS). We observe large variations in these energy-loss times that would make it extremely difficult to accurately evaluate and compare qubit fabrication processes and to perform studies that require precise measurements of energy loss. To address this issue, we present a technique for characterizing qubit quality factor. In this method, we apply a slowly varying electric field to TLS near the qubit to stabilize the measured energy relaxation time, enabling us to replace hundreds of hours of measurements with ones that span several minutes.


Fig. 2 Behavior of qubits containing alternative superconductors. Comparison of a quasiparticle tunnel rate and b quality factor Q = 2πf 01 T 1 of qubits with various designs and capacitor paddles composed of different superconductor materials such as Nb, Ta, Al, and NbN.
Fig. 3 Impact of qubit design on quasiparticle dynamics. a QPT rate vs. design in qubits with NbN paddles illustrating the nonlinear dependence of quasiparticle tunneling with increasing paddle dimensions, the inset shows the SEM images of tapered (D) and non-tapered (E) qubit designs, the scale bars correspond to 100 μm. b QPT rate vs. paddle area for the same qubits, c real part of the simulated qubit admittance which follows an exponential increase with paddle area, d comparison of mean values of experimentally obtained QPT rates for NbN and Al paddle qubits vs. simulated Re[Y(ω)].
Qubit parameters.
Quasiparticle tunneling as a probe of Josephson junction barrier and capacitor material in superconducting qubits
  • Article
  • Full-text available

December 2022

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177 Reads

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35 Citations

npj Quantum Information

Non-equilibrium quasiparticles are possible sources for decoherence in superconducting qubits because they can lead to energy decay or dephasing upon tunneling across Josephson junctions (JJs). Here, we investigate the impact of the intrinsic properties of two-dimensional transmon qubits on quasiparticle tunneling (QPT) and discuss how we can use quasiparticle dynamics to gain critical information about the quality of JJ barrier. We find the tunneling rate of the non-equilibrium quasiparticles to be sensitive to the choice of the shunting capacitor material and their geometry in qubits. In some devices, we observe an anomalous temperature dependence of the QPT rate below 100 mK that deviates from a constant background associated with non-equilibrium quasiparticles. We speculate that this behavior is caused by high transmission sites/defects within the oxide barriers of the JJs, leading to spatially localized subgap states. We model this by assuming that such defects generate regions with a smaller effective gap. Our results present a unique in situ characterization tool to assess the uniformity of tunnel barriers in qubit junctions and shed light on how quasiparticles can interact with various elements of the qubit circuit.

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Environmental radiation impact on lifetimes and quasiparticle tunneling rates of fixed-frequency transmon qubits

February 2022

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21 Reads

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61 Citations

Quantum computing relies on the operation of qubits in an environment as free of noise as possible. Assessing the quality of this environment is a key aspect of ensuring high-fidelity implementations based on superconducting qubits. Relaxation, decoherence, dephasing, and quasiparticle tunneling rates have been measured for various shielding configurations used in the measurement environment for state-of-the-art transmon qubits. An ensemble of approximately 120 control devices was used for this study, with five different capacitor pad designs. The shielding elements varied in the configuration included an indium gasket at the qubit can's lid, Cryoperm magnetic shielding, the mixing chamber shield of the dilution refrigerator, the inclusion of a vacuum pump-out port, and capping unused subminiature version A connectors at the top of the measurement can's lid. It was found that the qubit lifetimes T1, T2, and Tϕ are robust to the all of configuration changes tried until the mixing chamber shield was removed, significantly increasing blackbody radiation levels in the qubit measurement space, where in that limit it was found that tapering the qubit pads reduced the amount of loss. In contrast, the quasiparticle tunneling rates were found to be extremely sensitive to all configuration changes tested. Consistent with earlier reports [McEwen et al., arXiv:2104.05219 (2021); Cardani et al., Nat. Commun. 12, 2733 (2021); Wilen et al., Nature 594, 369–373 (2021); Ristè et al. Nat. Commun. 4, 1913 (2013)], the findings from this study indicate that non-equilibrium quasiparticles do not currently limit the lifetimes of well-shielded transmon qubits.


FIG. 2: Comparison of (a) quasiparticle tunnel rate and (b) quality factor of qubits with capacitor paddle metallization composed of different superconductor materials and geometries.
FIG. 3: (a) QPT rate vs. design in qubits with NbN paddles illustrating the nonlinear dependence of quasiparticle tunneling with increasing paddle dimensions, the inset shows the SEM images of tapered (D) and non-tapered (E) designs, the scale bar corresponds to 100 µm. (b) QPT rate vs. paddle area for the same qubits, (c) real part of the simulated qubit admittance which follows an exponential increase with paddle area, d) comparison of mean values of experimentally obtained QPT rates for NbN and Al paddle qubits vs. simulated Re[Y(ω)].
FIG. 4: a) Raw data of QPT rate vs. temperature for ten transmons with NbN capacitor paddles. The functional form of the temperature dependence shows significant variation despite that they share the same fabrication conditions. The inset is a cartoon showing the energy spectrum a junction where the barrier has high transmission regions across the junction. (b) Fits (black curves) to the QPT rate vs. temperature data (colored markers) showing good agreement and consistency of the inferred gaps from both models (c) The histograms built from fit parameters for various qubits with different type of paddle metallization.
FIG. 5: (a) Fits provided by the model in Eq.3 on the temperature dependence of the QPT data from nine qubits with Ta paddles.
FIG. 7: Cryogenic current-voltage measurements demonstrating the value of superconducting gap for Al thin film of the junctions
Quasiparticle tunneling as a probe of Josephson junction quality and capacitor material in superconducting qubits

June 2021

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116 Reads

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1 Citation

Non-equilibrium quasiparticles are possible sources for decoherence in superconducting qubits because they can lead to energy decay or dephasing upon tunneling across Josephson junctions. Here, we investigate the impact of the intrinsic properties of two-dimensional transmon qubits on quasiparticle tunneling (QPT) and discuss how we can use QPT to gain critical information about the Josephson junction quality and device performance. We find the tunneling rate of the non-equilibrium quasiparticles to be sensitive to the choice of the shunting capacitor material and their geometry in qubits. In some devices, we observe an anomalous temperature dependence of the QPT rate below 100 mK that deviates from a constant background associated with non-equilibrium quasiparticles. We speculate that high transmission sites within the Josephson junction's tunnel barrier can lead to this behavior, which we can model by assuming that the defect sites have a smaller effective superconducting gap than the leads of the junction. Our results present a unique characterization tool for tunnel barrier quality in Josephson junctions and shed light on how quasiparticles can interact with various elements of the qubit circuit.


Environmental Radiation Impact on Lifetimes and Quasiparticle Tunneling Rates of Fixed-Frequency Transmon Qubits

May 2021

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42 Reads

Quantum computing relies on the operation of qubits in an environment as free of noise as possible. This work reports on measuring the impact of environmental radiation on lifetimes of fixed frequency transmon qubits with various capacitor pad geometries by varying the amount of shielding used in the measurement space. It was found that the qubit lifetimes are robust against these shielding changes until the most extreme limit was tested without a mixing chamber shield in the refrigerator. In contrast, the quasiparticle tunneling rates were found to be extremely sensitive to all configurations tested, indicating these devices are not yet limited by losses related to superconducting quasiparticles.


Investigating surface loss effects in superconducting transmon qubits

May 2016

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4 Reads

Superconducting qubits are sensitive to a variety of loss mechanisms including dielectric loss from interfaces. By changing the physical footprint of the qubit it is possible to modulate sensitivity to surface loss. Here we show a systematic study of planar superconducting transmons of differing physical footprints to optimize the qubit design for maximum coherence. We find that qubits with small footprints are limited by surface loss and that qubits with large footprints are limited by other loss mechanisms which are currently not understood.


Density scaling with gate-all-around silicon nanowire MOSFETs for the 10 nm node and beyond

December 2013

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166 Reads

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94 Citations

Electron Devices Meeting, 1988. IEDM '88. Technical Digest., International

We present results from gate-all-around (GAA) silicon nanowire (SiNW) MOSFETs fabricated using a process flow capable of achieving a nanowire pitch of 30 nm and a scaled gate pitch of 60 nm. We demonstrate for the first time that GAA SiNW devices can be integrated to density targets commensurate with CMOS scaling needs of the 10 nm node and beyond. In addition, this work achieves the highest performance for GAA SiNW NFETs at a gate pitch below 100 nm.


High-performance Si1−xGex channel on insulator trigate PFETs featuring an implant-free process and aggressively-scaled fin and gate dimensions

January 2013

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239 Reads

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19 Citations

Digest of Technical Papers - Symposium on VLSI Technology

We demonstrate for the first time, Si1-xGex channel trigate PFETs on insulator with aggressively scaled fin width WFIN, gate length LG, and high-K/metal-gate stack (inversion oxide thickness TINV = 1.5 nm) using an implant-free raised source/drain (RSD) process. We report excellent electrostatic control down to LG = 18 nm for WFIN ≤ 18 nm. Using an optimized RSD process, we achieved high-performance SiGe-channel PFETs with oncurrent ION = 1.1 mA/μm at off-current IOFF = 100 nA/μm and supply voltage VDD = 1 V, which is attributed to high hole source injection velocity vx0 exceeding 1 × 107 cm/s.


Anisotropic capillary instability of silicon nanostructures under hydrogen anneal

March 2012

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26 Reads

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9 Citations

Anneal in reduced pressure hydrogen ambient is known to induce morphological changes in silicon microstructures via markedly increased surface self-diffusivity on exposed silicon surfaces. Here, we investigate the capillary instability of silicon nanostructures under hydrogen anneal. We demonstrate that a surface diffusion mask can significantly improve stability by isolating vulnerable segments from large mass reservoirs. In addition, we find that Plateau-Rayleigh instability shows strong crystallographic dependence, which is explained by the surface energy anisotropy of silicon. We observe that nanowires are the least stable when their axial orientation corresponds to 〈100〉 and are increasingly stable for 〈111〉, 〈112〉, and 〈110〉.


Fig. 1. The important role hydrogen -an n e a li ng plays in LER reduction.  
Fig. 10. Output voltage VOUT (left) and inverter current lvoo (right) vs. input voltage VIN of NW CMOS inverters.
Gate-all-around silicon nanowire MOSFETs and circuits

July 2010

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340 Reads

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12 Citations

We demonstrate undoped-body, gate-all-around (GAA) Si nanowire (NW) MOSFETs with excellent electrostatic scaling. These NW devices, with a TaN/Hf-based gate stack, have high drive-current performance with NFET/PFET IDSAT = 825/950 μA/μm (circumference-normalized) or 2592/2985 μA/μm (diameter-normalized) at supply voltage VDD = 1 V and off-current IOFF = 15 nA/μm. Superior NW uniformity is obtained through the use of a combined hydrogen annealing and oxidation process. Clear scaling of short-channel effects versus NW size is observed. Additionally, we observe a divergence of the nanowire capacitance from the planar limit, as expected, as well as enhanced device self-heating for smaller diameter nanowires. We have also applied this method to making functional 25-stage ring oscillator circuits.


Citations (41)


... Contemporary 3D cavities typically have very high-Q values (a measure of energy loss) exceeding 10 9 [20,46]. On the other hand, superconducting transmon qubits typically show Q values around 10 6 [45,47,48], but are nevertheless necessary to couple to the cavity in order to drive certain gates such as the SNAP gate. Hence we can safely ignore losses intrinsic to the cavity and assume that errors on the gates are primarily caused by the losses in the transmon. ...

Reference:

Benchmarking the performance of a high-Q cavity qudit using random unitaries
Quasiparticle tunneling as a probe of Josephson junction barrier and capacitor material in superconducting qubits

npj Quantum Information

... In superconducting circuits, the sources and measurement devices of the microwave field are typically connected to other components by dispersion-free coaxial or coplanar waveguides. These transmission lines act as dissipation channels, in addition to dielectric losses [72,73] or quasiparticles in the superconductors [74][75][76][77][78]. ...

Environmental radiation impact on lifetimes and quasiparticle tunneling rates of fixed-frequency transmon qubits
  • Citing Article
  • February 2022

... There is far less impurity doping in FinFETs than in MOSFETs. [3][4][5][6] FinFET has easy to control performance parameter, isolation present between adjacent devices and low power consumption, but it has complex to fabricate. [7][8][9][10][11][12][13] Nanowire FET is a new structure compared to MOSFETs and FinFETs, it has better gate controllability as gate is all around the channel, [14][15][16][17][18][19][20][21] high drive current and less subthreshold slope, but it has complex fabrication and greater parasitic capacitances. ...

High-performance high-k/metal gates for 45 nm cmos and beyond with gate-first processing
  • Citing Article
  • January 2007

... The TCAD simulator has been calibrated against experimental finding [24] to get the improved accuracy which is plotted in figure 2(a). Figure 2(b) presents the calibration of polarization (P) against electric field (E) which closely agrees with experimental values [25]. ...

Density scaling with gate-all-around silicon nanowire MOSFETs for the 10 nm node and beyond
  • Citing Conference Paper
  • December 2013

Electron Devices Meeting, 1988. IEDM '88. Technical Digest., International

... Moreover, the addition of phosphorus or boron precursors along with the Si precursor enables the growth of Si:P or Si:B alloys with much higher P or B doping concentrations than can be obtained via ion implantation [3][4][5][6]. In addition to Si, Group 4 elements such as Ge, C, etc. can be applied to stress engineering [7][8][9][10]. This enables a source/drain (S/D) strain engineering in which SiC epitaxy is used to increase electron mobility by providing tensile strain, while SiGe epitaxy is used to increase hole mobility by providing compressive strain. ...

High-performance Si1−xGex channel on insulator trigate PFETs featuring an implant-free process and aggressively-scaled fin and gate dimensions

Digest of Technical Papers - Symposium on VLSI Technology

... Fatigue in Si attracts much attention in the MEMS community because many of Si MEMS mechanical elements are subjected to cyclic stressing [36][37][38][39][76][77][78][79][80][81][82][83][84]. Kamiya et al. [78] did a Round Robin test to examine the S-N curve for Si. ...

Anisotropic capillary instability of silicon nanostructures under hydrogen anneal
  • Citing Article
  • March 2012

... B. H. Hong et al. [8] used the same methodology as [7], i.e. empirical fitting of interface trap charge parameter using only one interface trap level in the bandgap, but undoped channel was considered in [8]. Practical MOSFETs exhibit a range of SS values in the subthreshold region which equates to the presence of interface trap states distributed throughout the bandgap [9][10][11]. Therefore, for realistic modeling, it should not consider one interface trap level in the bandgap, but it should consider an interface trap distribution in the bandgap. ...

Interface state density measurements in gated p-i-n silicon nanowires as a function of the nanowire diameter
  • Citing Article
  • June 2010

... The silicon wafer then underwent the annealing process at 900 °C in a Nitrogen environment, and followed by dry oxygen in order to ensure that boron atoms are being spread properly in the wafer. The next step was to produce a Shallow Trench Isolator (STI) of 130 Å thickness [11]. In order to form the STI layer, the wafer was oxidized in dry oxygen for 25 minutes. ...

Challenges and Opportunities for High Performance 32 nm CMOS Technology
  • Citing Conference Paper
  • January 2007

... The HOT provides promising opportunities for the fabrication of MOSFET devices due to the significant performance boost provided by the use of (100)-orientated Si (the orientation in which the electron mobility is higher) and (110)-orientated Si (the orientation in which the hole mobility is higher) for n-and pMOSFETs, respectively [1], and a current flow in the 110 direction provides the highest drive currents for both types of devices [2]–[4]. Various implementations of this technology have been demonstrated by using silicon-on-insulator (SOI) substrates with either one [5] or both [6] types of devices on an insulating layer, but these solutions proposed for the implementation of the HOT on the SOI substrate require selective epitaxial growth, which involves significant process complexity and cost. On the other hand, the amorphization/templated recrystallization (ATR) integration scheme, which combines the direct silicon bond (DSB) substrate technology and the solid phase epitaxy (SPE), has been reported by fabricating devices on the bulk-Silike hybrid orientation substrate to easily reuse circuit design libraries from the bulk CMOS environment [7], [8]. ...

Silicon-on-Insulator MOSFETs with Hybrid Crystal Orientations
  • Citing Conference Paper
  • January 2006

... Sur SOI, la mémorisation de contrainte permet également d'augmenter le courant des nFET de 4 à 10 % [Singh05] [Hortsmann05] [Yin06]. L'utilisation successive de multiples techniques de SMT au cours de l'intégration permet d'augmenter encore plus la contrainte en tension dans le canal des nFET et ainsi d'atteindre un gain final de 27 % [Wei07]. ...

Integration of Local Stress Techniques with Strained-Si Directly on Insulator (SSDOI) Substrates
  • Citing Conference Paper
  • January 2006