Ishaan L. Dalal’s research while affiliated with University of Texas at Austin and other places

This paper presents a parallelized Quasi-Monte Carlo algorithm for the extraction of partial inductances in IC interconnect structures. Quasi-random numbers provide superior convergence over pseudo-random numbers, and in this paper the results are presented for three quasi-random number sequences-Halton, Sobol and Niderreiter. The algorithm has been parallelized and an almost linear rate of parallelization is achieved.

Computers face an ever increasing number of threats from hackers, viruses and other malware; effective Network Intrusion Detection (NID) before a threat affects end-user machines is critical for both financial and national security. As the number of threats and network speeds increase (over 1 gigabit/sec), users of conventional software based NID methods must choose between protection or higher data rates. To address this shortcoming, we have designed a hardware-based NID system-on-a-chip using data structures called Counting Bloom Filters (CBFs). Our design has extremely high throughput (up to 3.3 gigabits/sec) and can successfully detect and mitigate known threats, and is, to our knowledge, the only known CBF based NID system-on-a-chip to be implemented on a Virtex 4 FPGA. In this project, we present the first optimized, Counting Bloom Filter based Network Intrusion Detection FPGA SoC (system-on-chip) implemented on a Virtex 4 FPGA: our design is scalable through further parallelization and, to our knowledge, is one of the highest throughput NID systems in existence.

Low-discrepancy sequences, also known as ldquoquasi-randomrdquo sequences, are numbers that are better equidistributed in a given volume than pseudo-random numbers. Evaluation of high-dimensional integrals is commonly required in scientific fields as well as other areas (such as finance), and is performed by stochastic Monte Carlo simulations. Simulations which use quasi-random numbers can achieve faster convergence and better accuracy than simulations using conventional pseudo-random numbers. Such simulations are called Quasi-Monte Carlo. Conventional Monte Carlo simulations are increasingly implemented on reconfigurable devices such as FPGAs due to their inherently parallel nature. This has not been possible for Quasi-Monte Carlo simulations because, to our knowledge, no low-discrepancy sequences have been generated in hardware before. We present FPGA-optimized scalable designs to generate three different common low-discrepancy sequences: Sobol, Niederreiter and Halton. We implement these three generators on Virtex-4 FPGAs with varying degrees of fine-grained parallelization, although our ideas can be applied to a far broader class of sequences. We conclude with results from the implementation of an actual Quasi-Monte Carlo simulation for extracting partial inductances from integrated circuits.

Monte Carlo simulations and other scientific applications that depend on random numbers are increasingly implemented in parallel configurations in programmable hardware. High-quality pseudo-random number generators (PRNGs), such as the Mersenne Twister, are based on binary linear recurrence equations. They have extremely long periods (more than 2¹⁰²⁴ numbers generated before the entire sequence repeats) and well-proven statistical properties. Many software implementations of such dasialong-periodpsila PRNGs exist, but hardware implementations are rare. We develop optimized, resource-efficient parallel architectures for long-period PRNGs that generate multiple independent streams by exploiting the underlying algorithm as well as hardware-specific architectural features.

ABSTRACT Stochastic simulations and other scientific applications that depend on random,numbers,are increasingly implemented,in a parallelized manner,in programmable,logic. High-quality pseudo-random,num- ber generators (PRNG), such as the Mersenne Twister, are often based on binary linear recurrences and have extremely long peri- ods (more than 2,). Many software implementations,of such PRNGs exist, but hardware implementations are rare. We have developed an optimized, resource-efficient parallel framework for this class of random,number,generators that exploits the under- lying algorithm as well as FPGA-specific architectural features. The framework,also incorporates fast “jump-ahead” capability for these PRNGs, allowing simultaneous, independent sub-streams to be generated in parallel by partitioning one long-period pseudo- random,sequence. We demonstrate parallelized implementations,of three types of PRNGs – the 32-, 64- and 128-bit SIMD Mersenne Twister – on Xilinx Virtex-II Pro FPGAs. Their area/throughput performance,is impressive: for example, compared clock-for-clock with a previ- ous FPGA implementation, a “two-parallelized” 32-bit Mersenne Twister uses 41% fewer resources. It can also scale to 350 MHz for a throughput of 22.4 Gbps, which is 5.5x faster than the older FPGA implementation,and 7.1x faster than a dedicated software implementation. The quality of generated random,numbers,is veri- fied with the standard statistical test batteries diehard and TestU01. We also present two real-world application studies with multiple RNG streams: the Ziggurat method,for generating normal random variables and a Monte Carlo photon-transport simulation. The availability of fast long-period random,number,generators with multiple streams accelerates hardware-based scientific simu-

A design is presented for a multichannel integrated receiver/reconstruction system for MRI that alleviates the concerns associated with commercial solutions regarding cost, scalability and the ability to access intermediate data. Up to 16 MR signals are sampled directly at RF, with digital down-conversion and image reconstruction performed by a single-chip field-programmable gate array (FPGA). Imaging researchers can readily access data from any point in the processing chain over a network, and the design can scale modularly in blocks of 8n or 16n channels

Commercial receivers used for parallel MR imaging often present researchers with hurdles such as high cost-per-channel, low scalability for multiple coils and non-accessibility to intermediate data for research. A novel low-cost multichannel digital receiver for use with MR scanners has been developed to alleviate these concerns. MR signals from up to 16 coils are bandpass sampled at RF, with all subsequent downconversion performed on a single-chip Field-Programmable Gate Array (FPGA). Downconverted information is buffered and can be downloaded over a network or onto flash memory for image reconstruction. Arrays with more than 16 coils can easily scale by using more than one of these economical receivers. A 2-channel prototype has been designed, built and tested successfully with a combination of real-world signals and simulated MR data.

Parallel MRI acquisitions are generally reconstructed off-tine on PCs and computer clusters. Building upon an existing multichannel digital receiver, we present an innovative single-FPGA front-end that performs real-time 2D-FFT reconstruction from arrays of up to 16 coils. Partial reconfiguration enables rapid switching of FPGA modules for maximal flexibility and lower hardware cost. After an acquisition has been buffered, more complicated parallel MRI reconstruction techniques can replace receiver logic. Alternatively, the front-end can be used as a hardware-accelerated reconstruction engine with other receivers or for PCs. As proof-of-concept for real-time non-cartesian reconstruction, a reconfigurable module for next-neighbor regridding of spiral MRI is also demonstrated.

Abstract—Fast stream,ciphers,are,used,extensively,for en- crypted,data transmission,in mobile,networks,and,over multi- gigabit links. CryptMT, a recently proposed stream cipher, is one of the final candidates,for standardization,by the European Union’s eSTREAM project. Cryptanalysis,of CryptMT,has discovered,no attacks,or vulnerabilities thus far. We,present the,first hardware,implementation,of CryptMT,on,a,field- programmable,gate array (FPGA). On the Xilinx Virtex-2 Pro FPGA, throughputs of up to 16 Gbits/s can be obtained while using minimal,logic resources,(378 slices). This is highly area- efficient compared,to implementations,of ciphers such as AES and,RC4. Possibilities for parallelization and,scaling to higher throughputs,are also discussed.