Hugo Cavalaria’s research while affiliated with University of Algarve and other places

Ultra-low-power strategies have a huge importance in today's integrated circuits designed for internet of everything (IoE) applications, as all portable devices quest for the never-ending battery life. Dynamic voltage and frequency scaling techniques can be rewarding, and the drastic power savings obtained in subthreshold voltage operation makes this an important technique to be used in battery-operated devices. However, unpredictability in nanoscale chips is high, and working at reduced supply voltages makes circuits more vulnerable to operational-induced delay-faults and transient-faults. The goal is to implement an adaptive voltage scaling (AVS) strategy, which can work at subthreshold voltages to considerably reduce power consumption. The proposed strategy uses aging-aware local and global performance sensors to enhance reliability and fault-tolerance and allows circuits to be dynamically optimized during their lifetime while prevents error occurrence. Spice simulations in 65nm CMOS technology demonstrate the results.

The Internet of Things (IoT) paradigm is enabling easy access and interaction with a wide variety of devices, some of them self-powered, equipped with microcontrollers, sensors and sensor networks. Low power and ultra-low-power strategies, as never before, have a huge importance in today’s CMOS integrated circuits, as all portable devices quest for the never-ending battery life, but also with smaller and smaller dimensions every day. The solution is to use clever power management strategies and reduce drastically power consumption in IoT chips. Dynamic Voltage and Frequency Scaling techniques can be rewardingly, and using operation at subthreshold power-supply voltages can effectively achieve significant power savings. However, by reducing the power-supply voltage it imposes the reduction of performance and, consequently, delay increase, which in turn makes the circuit more vulnerable to operational-induced delay-faults and transient-faults. What is the best compromise between power, delay and performance? This paper proposes an automatic methodology and tool to perform power-delay analysis in CMOS gates and circuits, to identify automatically the best compromise between power and delay. By instantiating HSPICE simulator, the proposed tool can automatically perform analysis such as: power-delay product, energy-delay product, power dissipation, or even dynamic and static power dissipations. The optimum operation point in respect to the power-supply voltage is defined, for each circuit or sub-circuit and considering subthreshold operation or not, to the minimum power-supply voltage where the delays do not increase too much and that implements a compromise between delay and power consumption. The algorithm is presented, along with CMOS circuit examples and all the analysis’ results are shown for typical benchmark circuits. Results indicate that subthreshold voltages can be a good compromise in reducing power and increasing delays.

The low power quest in CMOS integrated circuits is pushing power-supply voltages to enter the subthreshold levels. The drastic power savings obtained in subthreshold voltage operation makes this an important technique to be used in battery-operated devices. However, working at subthreshold power-supply voltages, frequency operation has to be reduced, making Dynamic Voltage and Frequency Scaling (DVFS) methodologies hard to implement. In fact, existing solutions use wide safety margins and DVFS are typically implemented with static and pre-defined steps, both for the supply-voltage or the clock frequency. But changes in VDD and in clock frequency impose additional challenges, as delay faults may arise, especially in nanometer technologies. Moreover, when a PVTA (Process, power-supply Voltage, Temperature and Aging) variation occurs, circuit performance is affected and circuits are more prone to have delay-faults, especially when cumulative degradations pile up. This paper presents an improved version of the Scout Flip-Flop, the Low-power version, a performance Sensor for tolerance and predictive detection of delay-faults in synchronous digital circuits, which now can operate at power-supply subthreshold voltage levels. The sensor is based on a master-slave Flip-Flop (FF), the Scout FF, with built-in sensor functionality to locally identify critical operations, denoted here as in the eminence of an error, a performance error. The novelty of this solution is on the new architecture for sensor functionality, which allows the operation at VDDs’ subthreshold voltage levels. This feature makes Scout FF a unique solution to control DVFS and avoid delay-fault errors, allowing optimizing circuit operation and performance. To accomplish this, two distinct guard-band windows are created: a tolerance window; and a detection window. Simulations using a SPICE tool allowed characterizing the new sensor and flip-flop to work at sub-threshold voltages, and results are presented for a 65 nm CMOS technology, which uses Predictive Technology Models (PTM). The results show that the improved Scout’s version is effective on tolerance and predictive error detection, working at subthreshold voltages.