Heng Wu’s research while affiliated with IBM Research - Thomas J. Watson Research Center and other places

... Nanosheet field effect transistors (NSFETs) have become the flagship transistors driving the semiconductor industry from the 3 nm node and beyond [1]. Mitigating source/drain access resistance is a significant challenge in enhancing complementary metal-oxide-semiconductor (CMOS) device performance, particularly in advanced technology nodes, and there has been a continuous focus on researching and implementing strategies for achieving this [2]- [4], and hence it is crtical to consider access resistance while designing NSFETs. ...

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Predictive Simulation of Nanosheet Transistors Including the Impact of Access Resistance

... Considering that σ has a linear scaling behaviour with EOT and is inversely proportional to the channel area 26 , we compare Sσ(V th ) = σ(V th )(W g L g ) 1/2 SEOT/EOT, where W g is the gate width and SEOT is the scaled EOT set at 0.9 nm. The obtained Sσ(V th ) = 1.4 × 10 -7 V μm is among the lowest values reported to date 8,21,22,26,27,[46][47][48][49][50] . ...

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Two-dimensional semiconductor integrated circuits operating at gigahertz frequencies

... Utilizing a self-limiting growth mechanism, the layer-bylayer growth of conformal thin films in atomic layer deposition (ALD) methods has been used over large areas in recent years [27][28][29]. Various applications are processed with plasma-enhanced atomic layer deposition (PEALD) such as electrolytes in full cells [30,31], hard mask for protection in dry etching [32], optical applications [33], TiO 2 protected silicon photoanodes for water splitting [34], photocatalytic and photoelectrochemical applications [35,36], perovskite films for flexible solar cells [37] and deposition of superconducting niobium nitride [38]. In modern advanced semiconductor applications, the PEALD method is especially important [32] as the ultra-thin smooth layer leads to a feature size of a few nanometers [39,40], flexible metal oxide thin-film transistors [41]. ...

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Light Energy Transformation over a Few Nanometers

... It was indicated that single event responses of FinFET may be significantly affected by ion hit angular, position and energy, supply voltage, device size and number of fins, technology node, and so on 3,[5][6][7] . With the aggressive shrinking of device dimensions, spacer configuration and permittivity play the dominant roles in overall device performance [8][9][10][11][12][13][14] . It has been indicated that the device performance in terms of SS, current drivability, drain induced barrier lowering (DIBL) could be improved using an optimized spacer configuration 13,14 . ...

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Single event response of ferroelectric spacer engineered SOI FinFET at 14 nm technology node

... In particular, we demonstrate the method by focusing on ultraviolet ns-pulsed LA processes of SiGe, an alloy with composition-dependent electronic and optical properties [51][52][53] increasingly relevant to future nanoelectronic [3,28,[54][55][56][57][58][59], thermoelectronic [60], optoelectronic [8,61,62] and quantum technologies [2,[63][64][65]. The multiscale methodology provides unique atomistic insights on the complex and ultrafast morphological, compositional and structural transformations of SiGe during laser irradiation [19,20,66,67], giving invaluable support to process engineers aiming at the exploitation of this material's full potential. ...

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Atomistic Insights into Ultrafast SiGe Nanoprocessing

... Among them, low-temperature ozone passivation with low thermal budge and Si-cap passivation with excellent properties of interface are considered the most promising passivation methods. For example, the interface state density (D it ) of 2.2 × 10 12 eV −1 cm −2 Nanomaterials 2021, 11, 955 2 of 9 is attained by using a low-temperature ozone oxidation to passivate the interface of Al 2 O 3 /Si 0.7 Ge 0.3 [11],and the D it of 2 × 10 11 eV −1 cm −2 for the interface of HfO 2 /Si 0.8 /Ge 0.2 is realized by using a Si-cap passivation method [14]. However, the technique and mechanism of interface passivation of the HfO 2 /SiGe via low-temperature ozone oxidation or Si-cap method still needs further investigation. ...

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Investigate on the Mechanism of HfO2/Si0.7Ge0.3 Interface Passivation Based on Low-Temperature Ozone Oxidation and Si-Cap Methods

... Different kinds of technologies, such as anti-punch-through (APT) implantation, silicon on insulator (SOI), partial/full bottom dielectric isolation (BDI), and the narrow sub-Fin technique, have been proposed to suppress or totally cut off this leakage path [18][19][20][21]. Furthermore, several S/D design studies includingS/D confinement, trimming and doping concentration have also been addressed [22][23][24]. The device architecture of GAA FETs differs from that of FinFETs, so understanding the S/D recess impacts on the different leakage mechanisms along with Fin and NS FETs' performance comparison is essential for figuring out the optimal targets and most important process parameters [25]. ...

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Investigation of Source/Drain Recess Engineering and Its Impacts on FinFET and GAA Nanosheet FET at 5 nm Node