Hartmut Grabinski’s research while affiliated with Nanyang Technological University and other places

Electronic designers can timely design reliable and electromagnetic compatibility (EMC) compliant electronic systems if they focus on lowering emission levels from subsystems during design and development phases. In this paper, practical design rules, which designers should adhere to produce an EMC compliant system, are explained and their effects are demonstrated with the help of a demonstrator kit

Most design engineers still believe that with a good shielded enclosure, well-shielded cables and high-performance ferrite sleeves, EMI compliance will be a straight forward task. This paper demonstrates experimentally that a poor PCB layout can cause electronic product to fail EMI specification badly even with all these fixes

Transmission line models and material parameters are extracted from time and frequency domain measurements for product related low loss card and ceramic MCM test line structures up to 65GHz. All measured results are compared to results as obtained from field calculations showing the advantages and limitations of the different methods on product driven test vehicles.

This paper reports about a project for the creation of an innovative university course devoted to the preparation of future electronic designers to the challenges imposed by the assurance of the electrical performance of high-speed electronic systems. The target groups are future university teaching staff and future electronic systems designers. Activities are developed by means of sharing research results, seminars, experience exchange and the development of demonstrators to be used for teaching. The partnership is composed by Technical University of Turin (Italy), University of Hannover (Germany), University of Nottingham (UK), Nanyang Technological University (Singapore) and King Monguts Institute of Technology Lad-krabang, Bangkok (Thailand). The program is partially funded by the European Commission under the ASEAN-EU University Network Programme (AUNP) and its duration is 24 months.

The impact of the ground line position on the line parameters of signal interconnects built in a 110-nm CMOS technology is investigated in the presence of a conductive substrate. Characteristic line parameters obtained from simulations are validated with two-port network analyzer measurements of specially designed test structures in a frequency range up to 50 GHz. In addition, the influence of the ground line position on time-domain signals in product-related bus systems is explored. It is shown that the impact of substrate effects on the line parameters, and consequently on the signal shape in the time domain, strongly depends on the relative position of the ground line with respect to the signal lines and, as expected, on the length of the line system. The authors show that for short on-chip bus systems (shorter than 2 mm), the influence of the ground line positioning on time-domain signals is negligible. However, for long bus systems (e.g., 5 mm), this influence becomes significant and can no longer be neglected.

We investigate the impact of ground line position as well as the effects of conductive substrates with different conductivities of 10 S/m (low), 100 S/m (medium) and 10.000 S/m (high) on on-chip interconnects. Characteristic line parameters obtained from field calculations are validated with two-port network analyzer measurements of specially designed test structures in a frequency range up to 50 GHz.

S-parameter measurements were performed on special test lines embedded in an 8 copper metal layer test chip in order to determine the propagation constant y(f) and the complex characteristic impedance Z₀(f). Measurement results are presented for signal lines in the 7^th metal layer showing very good agreement with FEM-simulations in the frequency range up to 20 GHz.

The influence of the ground line position on the signal shape in the time domain is investigated in the presence of grounded substrates by M. F. Ktata et al. (2003) with different conductivities of 10 S/m (low) and 100 S/m (medium). It is shown that the impact of substrate effects on time domain signals depends on the substrate conductivity, on the relative position of the ground line with respect to the signal lines as well as on the length of the line system. In addition, the impact of process-related generated voids between closely spaced signal lines on crosstalk is investigated, too.

In this paper, we investigate the effects of floating and grounded substrates with different conductivities of 100 S/m (medium) and 10.000 S/m (high) on on-chip interconnections in the frequency range from 1 Hz up to 40 GHz. We show that the frequency dependency of line parameters, especially the inductance and resistance per unit length, depends strongly on whether the substrate is grounded or floating, on the relative position of the ground line with respect to the signal lines, and on the substrate conductivity.