Haleh Razavi’s research while affiliated with University of California, Berkeley and other places

What is this page?


This page lists works of an author who doesn't have a ResearchGate profile or hasn't added the works to their profile yet. It is automatically generated from public (personal) data to further our legitimate goal of comprehensive and accurate scientific recordkeeping. If you are this author and want this page removed, please let us know.

Publications (4)


Figure 2: SNOP cell at different stages of fabrication.a,b, SEM images of an as-made AAM with perfectly ordered pores (a) and a CdS nanopillar array after partial etching of the AAM (b). c, Transmission electron micrograph of the interface between a single-crystalline CdS nanopillar and a polycrystalline CdTe thin film. Inset: The corresponding diffraction pattern for which the periodically symmetric spots and multi-rings can be found. The symmetric spots are originated from the single-crystalline CdS nanopillar and the multi-rings are originated from the polycrystalline CdTe thin film.
Figure 3: Performance characterization of a representative SNOP cell.a, An optical image of a fully fabricated SNOP cell bonded on a glass substrate. b, I–V characteristics at different illumination intensities. c, The short-circuit current density, Jsc, shows a near-linear dependence on the illumination intensity, whereas the fill factor, FF, slightly decreases with an increase of the intensity. d, The open-circuit voltage, Voc, slightly increases with the intensity and the solar energy conversion efficiency is nearly independent of the illumination intensity for P=17100 mW cm-2.
Figure 4: Effects of the nanopillar geometric configuration on the device performance.a, Experimentally obtained efficiency of SNOP cells as a function of the embedded nanopillar height, H. NW: nanowire. The CdTe film thickness is maintained constant at 1 m.b, Theoretical simulation of the SNOP cell efficiency as a function of H, in qualitative agreement with the observed experimental trend shown in a. TF: thin film. Inset: Schematic diagram of the SNOP cell used for the simulation.c,d, Visualization of the Shockley–Read–Hall (SRH) recombination in SNOP cells with H=0 (c) and 900 nm (d). The space charge and carrier collection region is quite small when H=0 nm, resulting in a major carrier loss in the upper portion of the CdTe film through recombination, where there is a high EHP optical generation rate. However, the space charge and carrier collection region is significantly enlarged when H=900 nm; thus, the total volumetric carrier recombination loss is greatly reduced.
Figure 5: Mechanically flexible SNOP cells.a,b Schematic diagram (a) and optical image (b) of a bendable SNOP module embedded in PDMS.c,d, Theoretical simulation of the strain for a flexible SNOP cell (PDMS thickness 4 mm), showing only 0.01% maximum strain in the nanopillars. e, I–V characteristics of a flexible cell for various bending radii. f, Performance characterization of a flexible SNOP cell, showing minimal change in Voc and on bending of the substrate. The inset shows a picture of the set-up for bending the flexible modules.
Figure S1: The first (a) and second (b) imprint on an Al substrate with a straight line optical diffraction grating. (c) and (d) are SEM images of the AAM after first and second anodization steps, respectively.

+5

Three-Dimensional Nanopillar-Array Photovoltaics on Low-Cost and Flexible Substrates
  • Article
  • Full-text available

September 2009

·

674 Reads

·

1,018 Citations

Nature Materials

·

Haleh Razavi

·

Jae-won Do

·

[...]

·

Solar energy represents one of the most abundant and yet least harvested sources of renewable energy. In recent years, tremendous progress has been made in developing photovoltaics that can be potentially mass deployed. Of particular interest to cost-effective solar cells is to use novel device structures and materials processing for enabling acceptable efficiencies. In this regard, here, we report the direct growth of highly regular, single-crystalline nanopillar arrays of optically active semiconductors on aluminium substrates that are then configured as solar-cell modules. As an example, we demonstrate a photovoltaic structure that incorporates three-dimensional, single-crystalline n-CdS nanopillars, embedded in polycrystalline thin films of p-CdTe, to enable high absorption of light and efficient collection of the carriers. Through experiments and modelling, we demonstrate the potency of this approach for enabling highly versatile solar modules on both rigid and flexible substrates with enhanced carrier collection efficiency arising from the geometric configuration of the nanopillars.

Download

Fig. 1. Highly sensitive, direct band-gap NW photodiodes. (A) SEM (Top), schematic (Middle), and the band diagram (Bottom) of a CdSe NW photodetector with Ni/Pd Schottky S/D contacts. (B) I DS-VGS and IDS-VDS (Inset) curves of a representative CdSe NW device before (dashed, gray line) and after (solid, red line) white light illumination, exhibiting 100 times the current modulation. (C) Transient of a single CdSe NW device with an illumination intensity of 4.4 mW/cm 2 . (D) Illumination intensity-dependent measurements of a CdSe NW device, showing a nonlinear behavior.  
Fig. 4. Large-scale and heterogeneous integration of NWs for image sensing. (A) Optical image of an array of all-nanowire photodetector circuitry with each circuit element serving as an independently addressable pixel. (B) A defect analysis map showing the functional and defective NW photodetector circuit elements. (C) A histogram of the photocurrent for all functional circuit elements of the fabricated array. (D) An output response of the circuit array, imaging a circular light spot. The contrast represents the normalized photocurrent, with the gray pixels representing the defective sites (see SI Text).  
Large-Scale, Heterogeneous Integration of Nanowire Arrays for Image Sensor Circuitry

September 2008

·

122 Reads

·

248 Citations

Proceedings of the National Academy of Sciences

We report large-scale integration of nanowires for heterogeneous, multifunctional circuitry that utilizes both the sensory and electronic functionalities of single crystalline nanomaterials. Highly ordered and parallel arrays of optically active CdSe nanowires and high-mobility Ge/Si nanowires are deterministically positioned on substrates, and configured as photodiodes and transistors, respectively. The nanowire sensors and electronic devices are then interfaced to enable an all-nanowire circuitry with on-chip integration, capable of detecting and amplifying an optical signal with high sensitivity and precision. Notably, the process is highly reproducible and scalable with a yield of approximately 80% functional circuits, therefore, enabling the fabrication of large arrays (i.e., 13 x 20) of nanowire photosensor circuitry with image-sensing functionality. The ability to interface nanowire sensors with integrated electronics on large scales and with high uniformity presents an important advance toward the integration of nanomaterials for sensor applications.


Synthesis, Contact Printing, and Device Characterization of Ni-Catalyzed, Crystalline InAs Nanowires

July 2008

·

102 Reads

·

78 Citations

Nano Research

InAs nanowires have been actively explored as the channel material for high performance transistors owing to their high electron mobility and ease of ohmic metal contact formation. The catalytic growth of non-epitaxial InAs nanowires, however, has often relied on the use of Au colloids which is non-CMOS compatible. Here, we demonstrate the successful synthesis of high yield of crystalline InAs nanowires with high yield and tunable diameters by using Ni nanoparticles as the catalyst material on amorphous SiO2 substrates. The nanowires show superb electrical properties with field-effect electron mobility ~2,700 cm2/Vs and ION/IOFF >103. The uniformity and purity of the grown InAs nanowires are further demonstrated by large-scale assembly of parallel arrays of nanowires on substrates via the contact printing process that enables high performance, printable transistors, capable of delivering 5-10 mA ON currents (~400 nanowires). Comment: 21 pages, 5 figures included, all in .docx format. Nano Research (In Press)


Wafer-Scale Assembly of Highly Ordered Semiconductor Nanowire Arrays by Contact Printing

February 2008

·

175 Reads

·

579 Citations

Nano Letters

Controlled and uniform assembly of "bottom-up" nanowire (NW) materials with high scalability presents one of the significant bottleneck challenges facing the integration of nanowires for electronic applications. Here, we demonstrate wafer-scale assembly of highly ordered, dense, and regular arrays of NWs with high uniformity and reproducibility through a simple contact printing process. The assembled NW pitch is shown to be readily modulated through the surface chemical treatment of the receiver substrate, with the highest density approaching approximately 8 NW/mum, approximately 95% directional alignment, and wafer-scale uniformity. Such fine control in the assembly is attained by applying a lubricant during the contact printing process which significantly minimizes the NW-NW mechanical interactions, therefore enabling well-controlled transfer of nanowires through surface chemical binding interactions. Furthermore, we demonstrate that our printing approach enables large-scale integration of NW arrays for various device structures on both rigid silicon and flexible plastic substrates, with a controlled semiconductor channel width ranging from a single NW ( approximately 10 nm) up to approximately 250 microm, consisting of a parallel array of over 1250 NWs and delivering over 1 mA of ON current.

Citations (4)


... It is well-known that at the nanoscale, the properties of semiconducting materials change remarkably and have wonderful applications [1][2][3][4][5][6]. The photo-electrical characteristics of nanostructured semiconducting materials are one of the critical surface properties that are grabbing increased importance for applications in various fields such as photodetection, photovoltaics, biological sensing, gas sensing, etc [7][8][9][10][11][12][13][14][15][16]. In recent years, high-performance device fabrication based on such semiconducting materials has been focused on overcoming specific obstacles of some materials that limit/degrade the device's performance. ...

Reference:

Enhanced luminescence and visible-light photodetection performance of novel Bi, Sm, and Bi:Sm co-doped CdS nanostructured thin films developed via nebulizer spray pyrolysis technique
Three-Dimensional Nanopillar-Array Photovoltaics on Low-Cost and Flexible Substrates

Nature Materials

... The rapid advancement in high-resolution fabrication and transfer of nanoscale functional structures is driven by the demand for superior mechanical robustness and reliability, large-area uniformity, fast processing rates, all-dry processing conditions, low manufacturing costs, and crucially, conformal integration onto arbitrary substrates, including flexible, stretchable, and curvilinear surfaces, without compromising performance [1][2][3][4][5][6][7][8][9]. This demand is driven by the fastgrowing need for unconventional form factors in broad applications, including artificial skin [1], brain/machine interfaces [2], rollable and full-color displays [5,10], three-dimensional (3D)-stacked multilayer functional nanostructures, and heterodevices [11][12][13][14][15]. ...

Large-Scale, Heterogeneous Integration of Nanowire Arrays for Image Sensor Circuitry

Proceedings of the National Academy of Sciences

... The dry printing transfer method was utilized for fabricating the NWs array. The growth of donor substrate with as-grown NWs was flipped upside down and placed on the clean receiver SiO 2 substrate (n ++ Si wafer bearing 200 nm SiO 2 dielectric layer) 59,60 . After gently moving the donor substrate in one direction, the NWs will be separated from the growth substrates and laid down on the target substrate. ...

Wafer-Scale Assembly of Highly Ordered Semiconductor Nanowire Arrays by Contact Printing
  • Citing Article
  • February 2008

Nano Letters

... [150] Other examples of metals that have been used in the past include Sn for the growth of GaSb NWs [151] and Ni for InAs NWs. [152] However, the use of metals other than Au for this type of growth are far from being fully comprehended. As mentioned earlier, the use of Au can cause problems related to contamination of the nanostructures that renders them incompatible with CMOS electronics. ...

Synthesis, Contact Printing, and Device Characterization of Ni-Catalyzed, Crystalline InAs Nanowires

Nano Research