H. Xue’s scientific contributions

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Publications (3)


Granularity transformations based on a new CDFG format for granularity selection in hardware-software partitioning
  • Article

March 2005

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14 Reads

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3 Citations

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Y. Wang

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H. Xue

In this paper, granularity transformations based on a new CDFG format intended to support granularity selection in Hardware/Software partitioning are proposed. The transformations comprise the merge and expand operations, and use the hierarchical node as the transform bridge. Some requirements on the transformations are presented to maintain the syntax and semantics coherence of the system. The analysis shows that the proposed transformations are efficient, persistent and easy to implement. These features are suitable for the granularity selection in the Hardware-Software partitioning.


HCDFG-II - A representation of control/data flow graph for C language system specification

November 2004

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23 Reads

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2 Citations

An intermediate representation that is a hierarchical CDFG called HCDFG-II, and its transformation method are proposed. HCDFG-II, extended from the definition of HCDFG for software/hardware partition, is based on C language system specification. HCDFG-II introduces the memory accessing nodes to deal with the arrays and pointers of C program, and defines the concurrent structure to express the concurrent parts. At the same time, the transformation from C language to HCDFG-II becomes very easy since HCDFG-II adopts a control flow first structure. All these features provide more precise information for software/hardware partition, and make HCDFG-II an effective intermediate representation of C language specification.


Multi-way hardware-software partitioning algorithm based on abstract architecture template

November 2004

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16 Reads

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3 Citations

With the wide application of System-on-Chip in embedded system design, the hardware-software partitioning turns from a traditional bipartition problem to a multi-way partitioning problem. To deal with this issue, an abstract template of the processing element network connecting with communication channels is proposed for modeling multiple processing module architecture. Simulated annealing and heuristic scheduling algorithms are employed to determine the multi-way hardware-software partition and estimate the system performance and cost respectively. Preliminary experiments show that the proposed algorithm can make reasonable choice among different architectures for the optimization of system performance and cost.