H. Fujioka’s research while affiliated with Fukui University of Technology and other places

In Japan, stomach cancer is one of the three most common causes of death from cancer. Since periodic health checks of stomach X-rays have become more widely carried out, the physicians' burdens have been increasing in the mass screening to detect initial symptoms of a disease. For the purpose of automatic diagnosis, we try to develop a computer-assisted lesion detection system for stomach screening. The proposed system has two databases. One is the stomach shape database that consists of the computer graphics stomach 3D models based on biomechanics simulation and their projected 2D images. The other is the normal appearance database that is constructed by learning patterns in a normal patient training set. The stomach contour is extracted from an X-ray image including a barium filled region by the following steps. Firstly, the approximated stomach region is obtained by nonrigid registration based on mutual information. We define nonrigid transformation as one that includes translations, rotations, scaling, air-barium interface and weights of eigenvectors determined by principal components analysis in the stomach shape database. Secondly, the accurate stomach contour is extracted from the gradient of an image by using the Dynamic Programming. After then, stomach lesions are detected by inspecting whether the Mahalanobis distance from the mean in the normal appearance database is longer than a suitable value on the extracted stomach contour. We applied our system to 75 X-ray images of barium-filled stomach to show its validity.

A pattern matching technique between a scanning electron microscopy (SEM) exposed pattern image of large-scale integrated fine structures and computer-aided design (CAD) layout data based on the relaxation method is proposed wherein circular arc components are utilized. Edges are extracted from the SEM image and corners in the CAD layout are rounded. The edges in the SEM and CAD layout images are divided into three components: horizontal and vertical straight-line segments, and circular arcs. These components are expressed by bounding boxes; the optimal combination between the SEM and CAD components is then searched by using the probabilistic relaxation method. The mean vector among the obtained shift vectors shows the matching point. We applied our method to SEM exposed pattern images and compared the results with those of the conventional cross-correlation method. The results showed that our method has good robustness against change in shape of exposed pattern. The computation time of our method was comparable to the cross-correlation method.

An electron-beam direct writing (EBDW) system with a character projection (CP) aperture is a promising candidate as an effective maskless lithography tool to realize a system on a chip fabrication process at low cost with quick turn-around time. We have proposed an approach to enhance the throughput of an EBDW system by using a production dispatching rule. Through an event-driven simulation analysis in the backend of the line, the effect of production dispatching rules on the throughput and the cost in an EBDW system is evaluated. We considered four kinds of dispatching rules, FIFO, APA, LWKR, and SLACK. FIFO is a usually used dispatching rule and gives the highest priority to the waiting lot that came in first at the EB lithography process. In APA, the highest priority is given to the waiting lot that does not require the CP aperture exchange. In LWKR, the highest priority is given to the waiting lot associated with the job having the least amount of total processing time remaining to be done. In SLACK, the highest priority is given to the waiting lot with the shortest slack. Simulated result shows that the EBDW system with APA enhances the throughput more than 1.2 times as compared to that with FIFO, LWKR, or SLACK, and has a throughput of 5 wafers/h or more. Furthermore, compared with the cost per chip for FIFO, the APA rule reduces the cost/chip by more than 30% at the cost minimum lot arrival rate point.

The robustness of the cost-optimum sampling plan is evaluated by using the robustness evaluation procedure based on Taguchi methods. The procedure is a four-step approach: (1) design, (2) measurement, (3)SN analysis, and (4) analysis of variance (ANOVA) as to the result with the highest SN ratio. The contribution of each factor and the interaction between various factors of an experiment can be quantitatively determined by using ANOVA. Simulation study shows that the cost optimum combination of sampling plan and threshold gives the maximum robustness against many process fluctuations. When improving the noise factor with high contribution, the profit is increased by about 20%.

We have tried to optimize operator headcounts in the final test process of a one-chip microcomputer using a VLSI test process simulator with human factor to reply to an employment issue of how many new workers should be hired. The assumed final test process of a one-chip micro-computer has nine test flows that consists of fourteen stages at most. We select tasks for change kit exchanges and machine troubles as those required for a learning process. We simulate the work performance of newly hired workers by using the hyperbolic function with three parameters as a functional model of individual learning. According to the work performance value, we divide the learning process into three stages. The learning process for each stage differs according to relationships with expert workers. Our implemented event-driven simulator includes both processing-related and cost-related parameters. Simulations for two years were carried out for about total 2,400 lots/month. Result suggests that the manufacturing manager should hire new workers so that the ratio between newly hired and expert workers is about 1:2.

We have developed a three-dimensional eye movement simulator that simulates eye movement. The simulator allows us to extract the instantaneous eye movement rotation axes from clinical data sequences. It calculates the plane formed by rotation axes and displays it on an eyeball with rotation axes. It also extracts the innervations for eye muscles. The developed simulator is mainly programmed by a CG programming language, OpenGL. First, the simulator was applied to saccadic eye movement data in order to show the so-called Listing's plane on which all hypothetical rotation axes lie. Next, it was applied to clinical data sequences of two patients with benign paroxysmal positional vertigo (BPPV). Instantaneous actual rotation axes and innervations for eye muscle extracted from data sequences have special characteristics. These results are useful for the elucidation of the mechanism of vestibular symptoms, particularly vertigo.

We study on cost optimum embedded DRAM interconnect technologies by using a simple VLSI particle-induced fault simulator modified for the embedded DRAM macro. The fault simulator is applied to an assumed 4-Mbit DRAM macro production process with DRAM interconnect technologies of DRAM 1/2 pitch 115 nm and ASIC 1/2 pitch of from 115 nm to 500 nm (peripheral circuits). The DRAM macro is included in a SoC chip that has area of 1 cm² and is manufactured on the wafer with size of 8 inches. Result shows that the wider pitch decreases the count of manufactured chips but increases the yield. ASIC 1/2 pitch of 0.4 μm achieved maximum count of good chips per wafer under the assumed conditions. There exists the cost optimum embedded DRAM design.

An automatic LSI package lead inspection system for backside lead specification is proposed. The proposed system inspects not only lead backside contamination but also the mechanical lead specification such as lead pitch, lead offset and lead overhangs (variations in lead lengths). The total inspection time of a UQFP package with a lead count of 256 is less than the required time of 1 second. Our proposed method is superior to the threshold method used usually, especially for the defect between leads.

We have evaluated the final test process in a 64-Mbit DRAM manufacturing system through an event-driven simulation analysis concerning the number of chips simultaneously tested by a memory test system. Four test flows for DRAMS and SDRAMs are considered. The overall number of planned production chips during a month is 3 million. The number of chips simultaneously tested is 32, 64, 128, and 256. Simulations for six months were carried out as a function of number of memory test systems by using parameter values extracted from a real final test facility in Japan. From the overall assessments as to the average TAT and the cost per chip, the final test facility should have 14 memory test systems for this production plan where 128 chips are simultaneously tested.

In order to realize a system on a chip fabrication at low cost with quick turn-around-time, we have proposed a maskless lithography strategy, a low-energy electron-beam direct writing (LEEBDW) system with a common character projection (CP) aperture. This article presents a status report on our proof-of-concept (POC) system. We have developed a compact EB column consisting of small electrostatic lenses and deflectors. The experimental results for our POC system indicated that the patterns corresponding to 50-nm-node logic devices can be obtained with CP exposure at the incident energy of 5 keV. The technique to reduce the raw process time using a scanning electron microscope function of LEEBDW system is also reported. © 2002 American Vacuum Society.