Gerard Billiot’s research while affiliated with Cea Leti and other places

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Publications (2)


Power-Clock Generator Impact on the Performance of NEM-Based Quasi-Adiabatic Logic Circuits
  • Conference Paper

July 2015

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8 Reads

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2 Citations

Lecture Notes in Computer Science

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Gerard Billiot

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Marc Belleville

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[...]

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Herve Fanet

The influence of the power-clock generator on the global energy-performance relationship of nanoelectromechanical (NEM) switch-based quasi-adiabatic logic circuits is investigated in this paper. This investigation is undertaken the capacitor bank type generator, it is found that the leakage current of the MOSFET switching devices used within the generator constitutes an important source of performance degradation. Capacitor type generators are found to be most efficient for low operating frequencies (less than a MHz).


Limits of CMOS Technology and Interest of NEMS Relays for Adiabatic Logic Applications

June 2015

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63 Reads

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44 Citations

IEEE Transactions on Circuits and Systems I Regular Papers

In this paper, a detailed analysis and comparison of nanoelectromechanical systems (NEMS) and CMOS technologies for low power adiabatic logic implementation is presented. Fundamental limits of CMOS-based adiabatic logic are identified. Analytic relations describing the energy-performance for sub-threshold adiabatic logic are also explicitly derived and optimized. The interest of combining NEMS technology and adiabatic logic is described, and the key NEMS switch parameters that govern the dissipation-performance relationship are identified as the switch commutation frequency, its actuation voltage, and the contact resistance between the switch electrodes. Furthermore, NEMS-based adiabatic gates architectures are described. Finally, the contribution of the power-clock or energy recovery generator is estimated in order to compare CMOS and NEMS-based adiabatic architectures at the system level. The paper concludes with a detailed comparison of the energy-performance of the different explored technologies.

Citations (1)


... Finally, laterally actuated relays typically have a smaller footprint when compared to other relay structures. NEMS relays utilizing four and six-terminal configurations have also been proposed as logic gate building blocks to minimize the number of relays needed for any circuit path in logic circuits and thus the overall switching time for the desired logic function [11], [12], [13], [14]. The four terminal designs introduce an additional body bias terminal and two separate contact regions on the cantilever electrically isolated from the gate terminal which serves as the input, as can be seen in Figure 1 (c). ...

Reference:

Multi-Gate In-Plane Actuated NEMS Relays for Effective Complementary Logic Gate Designs
Limits of CMOS Technology and Interest of NEMS Relays for Adiabatic Logic Applications
  • Citing Article
  • June 2015

IEEE Transactions on Circuits and Systems I Regular Papers