Ganesh Garga's research while affiliated with Morphing Machines and other places
What is this page?
This page lists the scientific contributions of an author, who either does not have a ResearchGate profile, or has not yet added these contributions to their profile.
It was automatically created by ResearchGate to create a record of this author's body of work. We create such pages to advance our goal of creating and maintaining the most comprehensive scientific repository possible. In doing so, we process publicly available (personal) data relating to the author as a member of the scientific community.
If you're a ResearchGate member, you can follow this page to keep up with this author's work.
If you are this author, and you don't want us to display this page anymore, please let us know.
It was automatically created by ResearchGate to create a record of this author's body of work. We create such pages to advance our goal of creating and maintaining the most comprehensive scientific repository possible. In doing so, we process publicly available (personal) data relating to the author as a member of the scientific community.
If you're a ResearchGate member, you can follow this page to keep up with this author's work.
If you are this author, and you don't want us to display this page anymore, please let us know.
Publications (9)
QR decomposition (QRD) is a widely used Numerical Linear Algebra (NLA) kernel with applications ranging from SONAR beam forming to wireless MIMO receivers. In this paper, we propose a novel Givens Rotation (GR) based QRD (GR-QRD) where we reduce the computational complexity of GR and exploit higher degree of parallelism. This low complexity Column-...
The highest levels of security can be achieved through the use of more than one type of cryptographic algorithm for each security function. In this paper, the REDEFINE polymorphic architecture is presented as an architecture framework that can optimally support a varied set of crypto algorithms without losing high performance. The presented solutio...
Flexibility in implementation of the underlying field algebra kernels often dictates the life-span of an Elliptic Curve Cryptography solution. The systems/methods designed to realize binary field arithmetic operations can be tuned either for performance or for flexibility. Usually flexibility of these solutions adversely affects their performance....
In Dynamically Reconfigurable Processors (DRPs), compilation involves breaking an application into sub-tasks for piecewise execution on the fabric. These sub-tasks are sequenced based on data and control dependences. In DRPs, sub-task prefetching is used to hide the reconfiguration time while another sub-task executes. In REDEFINE, our target DRP,...
REDEFINE is a runtime reconfigurable hardware platform. In this paper, we trace the development of a runtime reconfigurable hardware from a general purpose processor, by eliminating certain characteristics such as: Register files and Bypass network. We instead allow explicit write backs to the reservation stations as in Transport Triggered Architec...
Flexible constraint length channel decoders are required for software defined radios. This paper presents a novel scalable scheme for realizing flexible constraint length Viterbi decoders on a de Bruijn interconnection network. Architectures for flexible decoders using the flattened butterfly and shuffle-exchange networks are also described. It is...
Building flexible constraint length Viterbi decoders requires us to be able to realize de Bruijn networks of various sizes on the physically provided interconnection network. This paper considers the case when the physical network is itself a de Bruijn network and presents a scalable technique for realizing any n-node de Bruijn network on an N-node...
In modern wireline and wireless communication systems, Viterbi decoder is one of the most compute intensive and essential elements. Each standard requires a different configuration of Viterbi decoder. Hence there is a need to design a flexible reconfigurable Viterbi decoder to support different configurations on a single platform. In this paper we...
To achieve the goal of efficient ”anytime, anywhere” communication, it is essential to develop mobile devices which can efficiently support multiple wireless communication standards. Also, in order to efficiently accommodate the further evolution of these standards, it should be possible to modify/upgrade the operation of the mobile devices without...
Citations
... This approach can be further improved by the column-wise Givens rotation where several elements of a column can be annihilated within the input matrix. This alteration has the advantage of fewer multiplications than the implementation of (Merchant et al., 2014(Merchant et al., , 2018. This also has the ability to combine coarseand fine-grained parallelism. ...
![[object Object]](https://i1.rgstatic.net/ii/profile.image/1003719676153856-1616316827366_Q64/Farhad-Merchant.jpg)
![[object Object]](https://i1.rgstatic.net/ii/profile.image/273631733350404-1442250297373_Q64/Anupam-Chattopadhyay.jpg)
![[object Object]](https://i1.rgstatic.net/ii/profile.image/307931017351169-1450427883874_Q64/S-Nandy.jpg)
... Dynamic logic reconfiguration is a concept that allows for efficient on-the-fly modifications of combinational circuit behavior in both ASIC [13,14] and FPGA devices. In FPGAs, combinational circuits are typically implemented using Look-Up Tables (LUTs), i.e., configurable primitives which store truth tables of k-input Boolean functions f : B k → B. Dynamic logic reconfiguration allows for the run-time alteration of the circuit behavior by modifying the content of specific look-up tables, while leaving the routing intact. ...
![[object Object]](https://i1.rgstatic.net/ii/profile.image/272395198005289-1441955484855_Q64/Saptarsi-Das.jpg)
... Garga et al. [9] have presented a scalable scheme for realizing reconfigurable VDs on a de Bruijn network based multiprocessor platform. In addition to de Bruijn, the architecture has also been implemented on shuffle-exchange and butterfly networks. ...
![[object Object]](https://i1.rgstatic.net/ii/profile.image/277229763350540-1443108134257_Q64/David-Guevorkian.jpg)
... Flexible constraint has the ability to improve the adaptability to the various demands in practical applications, such as the flexible constraint length Viterbi decoder [37]. For the supervised learning-based TS leaner, the key insight of introducing the flexible constraint into the design of training strategy is that: increasing the correlation between the training labels and the ground truth labels is helpful to improve the statistical power of the supervised learning-based TS leaner. ...
... Zhong and Willson [7] have implemented an energy efficient reconfigurable VD architecture on a programmable multiprocessor with a state-sequential approach in realizing the ACS operations. Rajore et al. [8] have presented a reconfigurable VD, realized on mesh connected multiprocessor platform. The architecture has been mapped onto a 9-node mesh connected NoC based MPSoC platform. ...
