Fredrik Allerstam’s research while affiliated with ON Semiconductor and other places

In this paper, 1.2 kV SiC trench MOSFET with deep P structure has been proposed to effectively shield the trench bottom oxide. The various design splits, such as N concentration between deep P and deep P to trench distance, were experimentally evaluated and TCAD simulations were performed to extract maximum oxide electric field at trench bottom. Based on trade off results, critical design parameters were optimized to obtain low Rdson and stable breakdown voltage with acceptable oxide electric field. To evaluate trench gate oxide reliability in wafer level, gate oxide integrity (GOI/Vramp), charge to breakdown (QBD), and time dependent dielectric breakdown (TDDB) tests were conducted. Also, high temperature gate bias (HTGB) and high temperature reverse bias (HTRB) stress tests were carried out for assembled samples to compare device reliability depending on different designs. For the target design, the promising reliability results were confirmed in both wafer level and assembled samples.

Device lifetime under reverse bias conditions is an important reliability concern for SiC devices. Provided that the termination structure is well designed, device failure in the active cell is driven by gate oxide breakdown due to the high field in the semiconductor and gate dielectric. For planar MOSFETs, the largest field occurs in the JFET region [1,2]. Standard HTRB testing is insufficient to estimate failure rates under operating conditions and hence testing under accelerated off-state conditions (ALT-HTRB) is required. This paper provides data, statistical analysis, failure analysis and finally a Weibull statistics-based temperature, Vd and stress time dependent model.

Novel diode structure which looks like DMOSFETs with the gate-shorted to n⁺ source has been developed for the first time. The lateral JFET channel as a built-in channel instead of gate oxide is integrated and it is pinched-off under the zero bias condition. As JFET diode decreases the forward voltage drop using JFET channel efficiency rather than the cell pitch reduction or the increase of doping concentration in n-SiC drift region, VF and capacitive charges which have a trade-off relationship typically could be decreased simultaneously and a better switching performance is also expected accordingly. Figure-of-Merit (=VF×QC) of the proposed JFET diode has been improved by 20.2% in average compared to that of JBS diode and this FOM would be the best in class among 1200V SiC diode products.

Unexpected behavior is observed when charge pumping is performed on silicon carbide MOSFETs with a thermally grown silicon dioxide gate dielectric. Supported by experimental evidence, two root causes are proposed: the trap density and the channel non-equilibrium. These are difficult to overcome experimentally due to limitations by oxide breakdown and doping variation along the channel, respectively. A correct interpretation then requires a 2D model.

Similar charge to failure distributions with mean values of about 50 C/cm ² were measured for planar SiC MOSFETs and MOS capacitors. Fast occurring and saturating negative flatband and threshold voltage drops were found in time resolved 1 second long pulsed gate current stress with I G =1 mA/cm ² at T=150 °C. No substantial difference in V TH drift rate with V GS =28 V at T=150 °C was found after about 10 s recovery period for I G stressed devices compared with unstressed devices. Additionally, I G stressed and unstressed devices did not differ in final V TH shift at T=25 °C after V GS =28 V stress (during 3 hrs or 31 hrs). More gate oxide reliability characterization is important to determine if 1 mA/cm ² pulsed gate current stress creates any permanent changes to the SiC MOSFET device behaviour. Additionally, parametric shifts in V TH and R DSon was examined after long-term AC gate bias stress by a gate driver switching between-8V and 20V for four different commercially available SiC MOSFETs.

This work details two approaches with multi-epitaxial growth to create a vertical superjunction structure made of alternating pillars. One approach is a chain of very high energy implants, the other uses a preferred implantation direction to achieve a channeled profile. The manufactured devices show a breakdown voltage of 1000 V for channeled, two-step epi with total 4.9 μm thickness. 800 V for regular high energy implants using three epi steps of total 3.7 μm thickness. The measured Rsp was 0.7 mOhm*cm ² for dies with size 0.018 cm ² . UIS and temperature measurement show reliable performance. The channeled implant looks favorable to reduce the number of process steps needed to create an efficient superjunction structure.

Gallium Oxide has undergone rapid technological maturation over the last decade, pushing it to the forefront of ultra-wide band gap semiconductor technologies. Maximizing the potential for a new semiconductor system requires a concerted effort by the community to address technical barriers which limit performance. Due to the favorable intrinsic material properties of gallium oxide, namely, critical field strength, widely tunable conductivity, mobility, and melt-based bulk growth, the major targeted application space is power electronics where high performance is expected at low cost. This Roadmap presents the current state-of-the-art and future challenges in 15 different topics identified by a large number of people active within the gallium oxide research community. Addressing these challenges will enhance the state-of-the-art device performance and allow us to design efficient, high-power, commercially scalable microelectronic systems using the newest semiconductor platform.

We have investigated the effect of high temperature annealing of phosphorus doped poly on gate oxide integrity and device reliability. In NMOS capacitance analysis, unstable flat band voltage characteristics and lower oxide breakdown electric field were observed in wafers which received high temperature poly annealing at 1100 °C. Gate oxide integrity (GOI/Vramp) tests and time dependent dielectric breakdown (TDDB) tests were performed to evaluate wafer level reliability. Degraded GOI characteristics and poor gate oxide lifetime were obtained for the high temperature poly annealed condition. To evaluate package level reliability, high temperature gate bias (HTGB) stress tests were conducted. Some samples failed in positive gate bias stress and more severe negative threshold voltage shift was observed in negative gate bias stress for the high temperature poly annealed condition.