Frank Brunner’s research while affiliated with Ferdinand-Braun-Institut and other places

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Publications (153)


K/Ka‐Band–GaN–High‐Electron‐Mobility Transistors Technology with 700 mS mm −1 Extrinsic Transconductance
  • Article

November 2024

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35 Reads

Physica Status Solidi (A) Applications and Materials

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Frank Brunner

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In this study, the impacts of fabrication technology and epitaxial layer design on the transconductance ( g m ) of radio frequency AlGaN/GaN high‐electron‐mobility transistors (HEMTs) are examined. Optimization of the SiN x passivation and AlGaN barrier design of 150 nm gate HEMTs enhances the extrinsic (at V ds = 10 V) and intrinsic (at V ds = 15 V) transconductance from ≈0.47/0.65 to ≈0.62/1.1 S mm ⁻¹ . Notably, an extrinsic g m of 0.70 S mm ⁻¹ at V ds = 5 V is achieved, setting a new benchmark for the extrinsic transconductance of AlGaN/GaN HEMTs designed for the K/Ka frequency range with a breakdown voltage exceeding 100 V.


Experimental Investigation of GaN-on-AlN/SiC Transistors With Regard to Monolithic Integration

October 2024

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58 Reads

IEEE Transactions on Power Electronics

The monolithic integration of the GaN-on-Si HEMTs is challenging since the back-gating effects caused by a common substrate degrade the device performance. In this paper, we introduce novel GaN-on-AlN/SiC power HEMTs. Compared with conventional GaN-on-Si HEMTs, the presented transistors show immunity to back-gating effects, thereby enabling monolithic integration of power devices without degradation of performance. Discrete power HEMTs are characterized systematically regarding both static and switching characteristics with a focus on the impact of the substrate potential. Furthermore, monolithic GaN-on-AlN/SiC half-bridges and monolithic GaN-on-AlN/SiC bidirectional switches are fabricated using the same device technology. The switching characteristics of these monolithically integrated devices are also investigated for different substrate terminations. It is demonstrated that both discrete and monolithically integrated devices achieve stable and fast switching and show a satisfactory back-gating immunity.


Figure 4. Measured contact resistance wafer maps from wafer W1 with a) non-implanted technology as reference b) implantation only under the ohmic contacts and c) full active area implanted. For b and c, Si with 1×10 15 cm -2 dose was implanted at 50 keV and activated by 8 min annealing at 1150°C in the MOCVD system. In each rectangle/shot (12.0 mm × 12.8 mm region), the value of one measured TLM is shown.
Figure 5. Measured contact resistance from wafers W1 and W2. Each wafer consists of TLM structures with different implantation schemes: non-implanted (reference), full active area or only area under the ohmic contacts were implanted . The dashed lines represent the mean value of all measured shots. The inserted values represent the mean of 45 shots (each shot containing one TLM structure) over a 4-inch wafer.
Figure 6. a) Transfer characteristics b) transconductance profile (gm) for fabricated 2×50 µm transistors. These devices have 150 nm gate length and respectively, 0.5 and 2.0 µm gate-source and gate-drain distances. c) On-state resistance and source resistance wafer distribution for the transistors shown in Figures 6a and 6b.
Figure 7. Further assessments of fabricated 2×50 µm transistors in terms of a) mean value of breakdown voltage versus Limp (see the inserted figure) for implanted and nonimplanted transistors from wafer W1 b) the total lag between Q1 (Vds=0 V, Vgs=0 V) to Q2 (Vds=20 V, Vgs=-7 V). Here, FBH baseline technology (reference) is compared with implanted and non-implanted devices from this work.
Si-implantation for low ohmic contact resistances in RF GaN HEMTs
  • Article
  • Full-text available

August 2024

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38 Reads

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1 Citation

In this work, Si implantation and activation for lowering the ohmic contact resistance (Rc) of mm-wave GaN HEMTs has been investigated. Various combinations of annealing temperature/duration and implantation doses were tested. Dopant activation was performed using a modified procedure in an MOCVD tool, involving fast temperature ramping and annealing the samples for 8 minutes at 1150 °C. Thereby, ~ 0.02 ± 0.01 Ω·mm contact resistance was achieved on a fully doped region and ~ 0.1 ± 0.02 Ω·mm when only the source and drain contact region was n-type doped. For comparison, a well-established alloyed Ti/Al/Ni/Au ohmic contact scheme without implantation, was used as reference resulting in an average Rc ~ 0.34 ± 0.12 Ω·mm on the same wafer. Besides the three times lowered contact resistance the implanted contacts also showed a significantly improved on-wafer homogeneity.

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1.17 GW/cm 2 AlN-based GaN-channel HEMTs on mono-crystalline AlN substrate

June 2024

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49 Reads

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1 Citation

IEEE Electron Device Letters

AlN-based GaN-channel HEMTs with MOCVD-grown AlGaN/GaN/AlN epistack were realized on AlN substrates, achieving 400 mA/mm current density at V GS = 1 V and 125 V/μm breakdown voltage (V Br ) scaling. Unlike for similar AlN-on-SiC devices, the high V Br scaling also applies above 1000 V. This is attributed to the significantly reduced AlN-buffer defect density. A record power density of 1.17 GW/cm 2 is extracted from a device with 2.2 kV breakdown voltage. High-voltage switching transients at 0.6 A / 464 V off-state voltage show dispersions effects attributed to the AlN-buffer/ GaN-channel interface quality.


Fig. 1: Surface modification by Ba(OH)2/MgO etching droplets. (a) Etched surface with radially symmetric roughness variation and debris. (b -e) Local variation of etch pit size from edge (b) to center (e) (sample F).
Fig. 3: SE and corresponding CL images of areas with etch pits for all AlxGa1-xN layers with 0 < x < 1. The positions of etch pits and dark spots match exactly. Distances dc from the center of the etched, circular areas to the respective measurement positions are mentioned.
Fig. 4: SE and corresponding CL image of an area of sample B that was only partially exposed to the defectselective etchant (lower right part). Dark spots in the etched and in the pristine regions appear identical.
Fig. 5: SE image and CL intensity maps of the same area for AlGaN (3.80 eV) and GaN (3.47 eV) emission from sample B. Spectrally resolved intensity data are derived from hyperspectral CL mappings. SE data, AlGaN and GaN emission are measured simultaneously. Positions of the etch pits are marked by red circles in the images.
Spatial correlation of defect-selective etching and dark luminescence spots in Al x Ga 1-x N

May 2024

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28 Reads

Defect-selective etching with molten Ba(OH) 2 /MgO etch drops was performed on c-plane AlGaN layers covering the entire composition range between GaN and AlN. Regardless of the aluminum content, the etchant produced shallow, hexagonal etch pits with depth-to-diameter ratios of 1/10 – 1/100. Two predominant types of etch pits were observed, which differed in size. In addition, the etch rate decreased from the center to the edge of the area exposed to the etch drops, providing a radially symmetric variation in etch pit size. For all AlGaN compositions, the positions of the etch pits correlate perfectly with the positions of the dark luminescence spots in cathodoluminescence measurements. Areas on the AlGaN samples that were not exposed to the etching procedure showed identical dark spots with the same size and density as those in the etched regions. Additionally, the density of etch pits and dark spots corresponded to the density of threading dislocations in the AlGaN layers. These observations demonstrate that the density of threading dislocations in c-plane AlGaN layers can be determined by destructive defect-selective etching with Ba(OH) 2 /MgO and etch pit counting, as well as by nondestructive counting of the dark spots in cathodoluminescence images.


GaN Drift Layers on Sapphire and GaN Substrates for 1.2 kV Class Vertical Power Devices

March 2024

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75 Reads

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1 Citation

physica status solidi (RRL) - Rapid Research Letters

The development of processes for epitaxial growth of vertical gallium nitride (GaN) drift layers enabling 1.2 kV breakdown voltage on low‐cost sapphire substrates is presented in comparison to GaN bulk substrates. The targeted blocking capability demands drift layers with a thickness of 10 μm and low but controllable n‐type doping. Using a growth rate of 2.5 μm h ⁻¹ the concentration of unintentionally incorporated carbon is sufficiently low to adjust the n‐type carrier concentration to ≈1 × 10 ¹⁶ cm ⁻³ for all types of substrates. To assess GaN drift region properties in terms of forward bias conductivity and reverse bias blocking strength, a quasi‐vertical p‐n‐diode structure is utilized. Bow reduction of GaN‐on‐sapphire structures is achieved using a stealth laser scribing process. Breakdown voltages higher than 1600 V and a specific on‐state resistance as low as 0.7 mΩ cm ² are obtained with diodes fabricated on GaN substrates. Similar structures grown on sapphire show breakdown voltages of about 1300 V due to higher levels of current leakage. Comparing different types of substrates, a direct correlation between dislocation density in the drift layer with the leakage current in p‐n diodes is deduced.


Investigation of atomic layer deposition methods of Al2O3 on n-GaN

February 2024

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68 Reads

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1 Citation

In this work, three atomic layer deposition (ALD) approaches are used to deposit an Al2O3 gate insulator on n-GaN for application in vertical GaN power switches: thermal ALD (ThALD), plasma-enhanced ALD (PEALD), and their stacked combination. The latter is a novel method to yield the most ideal insulating layer. Also, the influence of an in situ NH3 or H2 plasma pre-treatment is studied. Planar MIS capacitors are used to investigate the electrical properties and robustness of the gate insulators. In vacuo x-ray photoelectron spectroscopy (XPS) is used to study the changes in chemical composition after every surface treatment. XPS shows that all plasma pre-treatments efficiently remove all carbon contamination from the surface, but only NH3 plasma is observed to additionally remove the native oxide from the n-GaN surface. The water precursor step in the ThALD process does not completely remove the CH3 ligands of the trimethylaluminum precursor step, which might electrically be associated with a reduced forward bias robustness. The O2 plasma step in the PEALD process is associated with the removal of carbon and a tremendous increase of the O content in the GaN surface region. Electrically, this strongly correlates to an enhanced forward bias robustness and an increased forward bias hysteresis, respectively. The ThALD/PEALD stack method mitigates the shortcomings of both ALD processes while maintaining its advantages. Electrical measurements indicate that the stack method alongside NH3 plasma pretreatment provides the best characteristics in terms of hysteresis, threshold voltage, forward bias robustness, and interface trap density of states.



10 A/950 V switching of GaN-channel HFETs with non-doped AlN buffer

May 2023

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59 Reads

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5 Citations

AlN-based semiconductor devices are considered to outperform lateral AlGaN/GaN HFETs for power-electronic switching applications due to the high AlN-material breakdown field strength. We present an AlGaN/GaN/AlN-HFET transistor without any compensation doping in the AlN-buffer layer. Breakdown voltage scaling as function of the gate-drain separation of 140 V/µm and power figure-of-merit of 2.4 GW/cm2 were achieved which is superior to most other GaN device technologies. 120 mΩ power transistors demonstrated 10 A switching transients up to 950 V off-state voltage and thus meet basic requirements for kW-range power switching. The origin of still present dispersion effects during high voltage switching could be attributed to a high structural defect density at the AlN-buffer / GaN channel material interface.



Citations (75)


... Nevertheless, owing also to their lower maturity, vertical GaN devices are expected to suffer from chargetrapping related issues. These issues critically affect both conduction and switching losses because of the degradation of key electrical parameters (i.e., VT [7], RON [15], as well as device capacitances [16]). In general, trapping mechanisms can be classified depending on: (i) the specific trap parameters determining their dynamics, (ii) the location of the traps within the complex device structure, (iii) the type of carriers being captured/emitted, and (iv) the charging/discharging path of the trap [2]. ...

Reference:

Experimental and Numerical Analysis of Off-State Bias Induced Instabilities in Vertical GaN-on-Si Trench MOSFETs
Correlating Interface and Border Traps With Distinctive Features of C – V Curves in Vertical Al2_{\text{2}}O3_{\text{3}}/GaN MOS Capacitors

IEEE Transactions on Electron Devices

... Moreover, the ultrawide bandgap material AlN used as a buffer layer with higher bandgap and thermal conductivity compared to GaN enables an efficient back-barrier and channel confinement in high voltage applications and better thermal management in the lateral structure [23], [24]. A high breakdown voltage of 1790 V was measured on-wafer for the presented transistors with a gate-drain length d gd = 15 µm and indicates their potential to achieve high-voltage operation, as presented in [25]. ...

10 A/950 V switching of GaN-channel HFETs with non-doped AlN buffer
  • Citing Conference Paper
  • May 2023

... The temperature-dependent thermal properties of semiconductors are considered. Table 1 lists the thermal conductivities and electric conductivities of the materials used in the simulations [22,23]. All calculations in this work are based on the finite-element method (FEM) as implemented in COMSOL multiphysics. ...

Thermal management of vertical GaN transistors
  • Citing Conference Paper
  • April 2023

... Vertical GaN technology grown on low-cost foreign substrates is a promising solution for medium-and high-voltage applications. This technology relies on junctions to provide high and reliable performance while potentially allowing a low cost of fabrication [3][4][5][6][7][8]. In this frame, GaN P-N junction-based vertical structures offer Micromachines 2024, 15, 1157 2 of 10 robust performance including avalanche breakdown capability and high current spreading while maintaining small device dimensions [3,9,10]. ...

Optimization of Vertical GaN Drift Region Layers for Avalanche and Punch-Through Pn-Diodes
  • Citing Article
  • March 2023

IEEE Electron Device Letters

... However, we have found that crystallization of a sputtered AlN cap-layer during high-temperature annealing prevents its removal by wet etching (in c-oriented crystals) [25][26]. Using plasma etching is also not feasible since it might damage the epitaxial layers beneath and reduce conductivity of the 2DEG channel [27]. Here, we use an MOCVD-grown 2-3 nm thick silicon nitride layer for capping which is grown at 800 to 1000 °C. ...

Analysis of Mechanical Strain in AlGaN/GaN HFETs
  • Citing Article
  • December 2022

Physica Status Solidi (A) Applications and Materials

... 21,[24][25] To mitigate these issues, various thermal annealing strategies are currently explored at different stages of the MIS device fabrication, either after the ALD deposition 18 [Post-Deposition-Annealing (PDA)] or after the deposition of the metal gate [Post-Metallization-Annealing (PMA)]. 19 Tadmor et al. 26 suggested that the annealing process of Al 2 O 3 /GaN systems should not exceed 550 ○ C to avoid the Al 2 O 3 degradation as the CV-instability demonstrated. In this perspective, Hashizume et al. 20,27 treated the Al 2 O 3 /GaN system to a PMA process at 300-400 ○ C in N 2 , demonstrating that such a treatment is beneficial for the electrical performance of the dielectric/GaN system inducing a notable decrease in the interface trap density (D it ). ...

Effects of post metallization annealing on Al 2 O 3 atomic layer deposition on n -GaN

... The ohmic contact resistance (Rc) is a key parameter that directly impacts RF performance of GaN HEMTs via characteristics such as cut-off frequency, maximu m oscillation frequency, noise figure, and knee voltage [1][2]. To reduce Rc different approaches such as recess etching/thinning of the AlGaN barrier to facilitate top [3] or side [4] connection of the ohmic contact metal to the 2DEG channel, ion implantation (0.2 Ω·mm [5]) and the regrowth of a highly doped GaN layer in contact regions [6][7] are considered. ...

Au‐Free Ohmic Contact for GaN HEMTs
  • Citing Article
  • February 2022

Physica Status Solidi (A) Applications and Materials

... 29,32,33 The dark spot diameter in CL mapping and its temperature dependence have been compared for GaN and AlGaN epitaxial layers, and the effect of carrier localization has been discussed. 34 The effects of dislocations and point defects acting as nonradiative recombination centers on IQE have also been studied in detail by temperaturedependent analysis of the CL intensity line profile around dark spots and PL measurements in AlN epitaxial films and the Al-rich AlGaN MQW structure. 35 In this study, AlGaN MQWs were prepared on an FFA Sp-AlN template with different IQEs and similar dislocation densities, and the correlation between the IQE and the effective diffusion length estimated by the CL intensity line profile near the dark spots, including the effect of non-radiative recombination due to point defects, was experimentally clarified. ...

Temperature Dependence of Dark Spot Diameters in GaN and AlGaN
  • Citing Article
  • August 2021

physica status solidi (b)

... In this article, we present GaN-on-AlN/SiC transistors fabricated on a semi-isolating SiC substrate using an AlN buffer layer, which suppresses back-gating effects and thus is capable of achieving monolithic integration without performance degradation. Moreover, the ultrawide bandgap material AlN used as a buffer layer with higher bandgap and thermal conductivity compared to GaN enables an efficient back-barrier and channel confinement in high voltage applications and better thermal management in the lateral structure [23], [24]. A high breakdown voltage of 1790 V was measured on-wafer for the presented transistors with a gate-drain length d gd = 15 µm and indicates their potential to achieve high-voltage operation, as presented in [25]. ...

GaN-channel HEMTs with AlN buffer for high-voltage switching
  • Citing Conference Paper
  • June 2021

... Consequently, applying Equation (3) with the parameters in Table 1 leads to traction of the effective trench bottom and channel mobilities of 15.1 and 11.1 respectively. As explained in [25], this poor channel mobility value could be ma lated to the damaged trench sidewalls following the GaN trench etching step, wh critical process step for the fabrication of vertical GaN trench MOSFETs [7,26,2 should result, on the one hand, in carrier scattering coming from surface rough seen in Figure 2b), and on the other hand, in oxide interface traps at the dielect After removing the R S contribution (measured with TLMs as being around~13 Ω·mm for one source electrode) from the R tot , and by considering the thickness of the p-GaN layer, we estimated a channel sheet resistance R sheet,ch of~91.0 kΩ·sq. ...

On the Conduction Properties of Vertical GaN n-Channel Trench MISFETs

IEEE Journal of the Electron Devices Society