Francois Atallah’s research while affiliated with Qualcomm and other places

A 7-nm register file (RF) with a 16-transistor (16T) 3-read and 3-write (3R3W) bitcell double pump or time multiplexes the read and write access ports twice per clock cycle to achieve 6-read and 6-write (6R6W) operations per cycle for high-bandwidth (BW) on-die memory in high-performance machine learning and CPU processors. From silicon test-chip measurements at 0.9 V, the double-pumped (DP) 6R6W RF trades off a 19% lower maximum clock frequency ( $F_{\mathrm{ MAX}}$ ) for $2\times$ the number of read and write operations per cycle, resulting in a 62% higher memory BW compared to a conventional single-access (SA) 3R3W RF.

Static power consumes a significant portion of the available power budget. Consequently, leakage current reduction techniques such as power gating have become necessary. Standard global power gating approaches are an effective method to reduce idle leakage current, however, global power gating does not consider partially idle circuits and imposes significant delay and routing constraints. An adaptive power gating technique is applied locally to a 32-bit Kogge Stone adder, and evaluated at the 16 nm FinFET technology node. This high granularity adaptive power gating approach employs a local controller to lower energy use and reduce circuit overhead. The controller conserves additional power when the circuit is partially idle (based on the inputs to the adder) by adaptively powering down inactive blocks. Moreover, the local controller reduces routing complexity since a global power gating signal is not required. The proposed adaptive power gating technique exhibits significant energy savings, ranging from 8% to 21%. This technique targets partially idle circuits, and therefore complements rather than replaces global power gating techniques. A 12% delay overhead results in a 5% area overhead. This delay overhead is reduced to 5% by increasing the area overhead to 16%, and can be further reduced by trading off additional area.

A 16 nm all-digital auto-calibrating adaptive clock distribution (ACD) enhances processor core performance and energy efficiency by mitigating the adverse effects of high-frequency supply voltage (VDD) droops. The ACD integrates a tunable-length delay prior to the global clock distribution to prolong the clock-data delay compensation in core paths for multiple cycles after a droop occurs to provide a sufficient response time for clock frequency (FCLK) adaptation. A dynamic variation monitor (DVM) detects the onset of the droop and interfaces with an adaptive control unit and clock divider to reduce FCLK in half at the TLD output to avoid path timing-margin failures. An auto-calibration circuit enables in-field, low-latency tuning of the DVM to accurately detect VDD droops across a wide range of operating conditions. The auto-calibration circuit maximizes the VDD-droop tolerance of the ACD while eliminating the overhead from tester calibration. From 109 die measurements across a wafer, the auto-calibrating ACD recovers a minimum of 90% of the throughput loss due to a 10% VDD droop in a conventional design for 100% of the dies. ACD measurements demonstrate simultaneous throughput gains and energy reductions ranging from 13% and 5% at 0.9 V to 30% and 13% at 0.6 V, respectively.

System-on-chip (SoC) processor cores experience high-frequency supply voltage (VDD) droops when the current in the power delivery network abruptly changes in response to workload variations, thus degrading performance and energy efficiency. Previous adaptive circuit techniques aim to reduce the effects of VDD droops by sensing the VDD variation with an on-die monitor and adjusting the clock frequency (FCLK) [1-2] or by directly modulating the phase-locked loop (PLL) clock output with changes in the core VDD to implicitly adapt FCLK [3]. The adaptive response time and complex analog circuits limit the benefits of these techniques for a wide range of FCLK and VDD operating conditions. The adaptive clock distribution (ACD) [4-5] exploits the path clock-data delay compensation during a VDD droop to enable a sufficient response time to proactively adapt FCLK. Although the ACD mitigates the impact of VDD droops on performance and energy efficiency, the previous designs require extensive post-silicon tester calibration of the dynamic variation monitor (DVM) to accurately detect the onset of the VDD droop. Since SoC cores operate across a wide range of FCLK, VDD, temperature, and process conditions, the DVM requires a unique calibration for each operating point, thus resulting in prohibitively expensive test time for high-volume products. This paper describes an ACD design in a 16nm [6] test chip with an auto-calibration circuit to enable in-field, low-latency tuning of the DVM across a wide range of operating conditions to maximize the ACD benefits, while eliminating the costly overhead from tester calibration.