E. Leobandung’s research while affiliated with IBM Research - Thomas J. Watson Research Center and other places

What is this page?


This page lists works of an author who doesn't have a ResearchGate profile or hasn't added the works to their profile yet. It is automatically generated from public (personal) data to further our legitimate goal of comprehensive and accurate scientific recordkeeping. If you are this author and want this page removed, please let us know.

Publications (89)


Figure 9. (a) Hardware -timing and data out and bit fail map of SRAM, (b) Bit Fail map with VCSmin of 0.45V, (c) VCS-VDD shmoo with VCSmin=0.45V
SRAM and Mixed-Signal Logic With Noise Immunity in 3nm Nano-Sheet Technology
  • Article
  • Full-text available

January 2025

·

14 Reads

IEEE Open Journal of the Solid-State Circuits Society

Rajiv V. Joshi

·

J. Frougier

·

Alberto Cestero

·

[...]

·

E. Leobandung

A modular 4.26Mb SRAM based on a 82Kb/block structure with mixed signal logic is fabricated, characterized, and demonstrated with full functionality in a 3nm nanosheet (NS) technology. Designed macros utilize new circuits for supply boosting, read, and write assist techniques. The proposed circuits are evaluated extensively and compared to prior techniques. Statistical simulations are used to predict the benefits of these circuits in the context of dual supply use. Through programmable local clock and wordline (WL) pulsewidths, SRAM cell margins and speeds are demonstrated through hardware measurement. Stability assists as well as dual supply techniques are used to demonstrate how noise can be suppressed during traditional memory operations (single WL on), as well as to support mixed-signal logic block operation (multiple WLs on). Functionality is shown down to a cell supply of 0.45V with an estimated margin/speed of 6 GHz for SRAM cells (High Density-0.026μm2, and High Current -0.032μ m2).

Download










Citations (56)


... Setting the threshold voltage for FinFETs and GAA FETs. To set the proper threshold voltage for the lowest operation voltage and off-state current at cryogenic temperature, approaches adopted in advanced technologies, including selection of metal work functions, dipole formation and bandgap engineering of channels, are still valid at cryogenic temperature 4,89 (Fig. 2i). Dipoles can be formed either before (dipole-first) or after (dipole-last) high-k dielectric deposition. ...

Reference:

Ultra-low-power cryogenic complementary metal oxide semiconductor technology
High Performance Nanosheet Technology Optimized for 77 K
  • Citing Conference Paper
  • December 2023

... Strong p-type MOSFETs based on III-V material is essential for future logic implementation and their integration with state-ofthe-art n-type RF transistors. Combinations of more conventional p-type SiGe channel devices integrated with ntype III-V InGaAs based devices has been proposed [9], [10]. However, material selectivity during processing may limit this type of material integration, which motivates further studies and development of III-V based p-type transistors. ...

Demonstration of record SiGe transconductance and short-channel current drive in High-Ge-Content SiGe PMOS FinFETs with improved junction and scaled EOT
  • Citing Conference Paper
  • June 2016

... At such narrow WFIN, the carrier transport is influenced by the quantum confinement as well as the mobility degradation along the transport direction. The p-type devices have reported to have reduced mobility possibly due to these reasons [21]. Although transport along (110)/<110> are preferred for superior hole mobility [22], it still reduces for the p-FinFETs as compared to n-FinFETs at high inversion charge densities with reduced WFIN [23]. ...

Replacement high-K/metal-gate High-Ge-content strained SiGe FinFETs with high hole mobility and excellent SS and reliability at aggressive EOT ∼7Å and scaled dimensions down to sub-4nm fin widths
  • Citing Conference Paper
  • June 2016

... However, the NWs are encapsulated heavily with parasitic components [8]. Also, the reduced silicon area reduces the effective drive current (I eff ) at any given fin height [9], [10]. In contrast, the GAA nanosheet (NS) has increased silicon area and can provide increased currents, however, once again, consumes more silicon footprint and loses the subthreshold control [11]. ...

Critical Elements for Next Generation High Performance Computing Nanosheet Technology
  • Citing Conference Paper
  • December 2021

... However, due to the nature of RPU-based stochastic multiplication, this type of training algorithm is mainly relevant for clocked spiking systems where voltage pulses can align in time for predictable periods of time (i.e. a clock cycle). This is the case because we are using an RPU-based approach which requires pulse co-incidence to update the weights and is a common assumption for RPUcapable memories proposed as synapses, including analog memories [31], [23], [47], [48], [49]. As such, pulse-extender circuits, such as ones described in works such as [37], [50], [51] would be required to interface data from asynchronous AER sensors with our RPU-based SNN learning system Several device-level implementations of stochastic neurons using resistive memories like phase change memories [52], bulk switching PCMO RRAMs [53] and nanomagnets [54] have been proposed. ...

Unassisted True Analog Neural Network Training Chip
  • Citing Conference Paper
  • December 2020

... Another advantage of VLS grown NWs is, that they allow for crystal phase tuning [55,56] with the principal growth direction along [111]zincblende (ZB) or [0001] wurtzite (WZ), which is not generally the case in TASE and ART. ...

High Performance InGaAs Gate-All-Around Nanosheet FET on Si Using Template Assisted Selective Epitaxy
  • Citing Conference Paper
  • December 2018

... To achieve this, the ideal analog resistive device should exhibit bidirectional, linear, and symmetric conductance updates in response to an open-loop programming pulse scheme (i.e., without the need for verification following each pulse) [4,14]. Promising technologies include redox-based resistive switching memory (ReRAM) [15,16], electro-chemical random access memory (ECRAM) [17], and capacitive weight elements [18]. Addressing the various non-idealities of these technologies [19] requires the co-optimization of technology and designated training algorithms. ...

Capacitor-based Cross-point Array for Analog Neural Network with Record Symmetry and Linearity
  • Citing Conference Paper
  • June 2018

... The data shown in Fig. 4 were measured on an FET with a channel width of 100 µm, and gate length of 10 µm at low V DS = 50 mV to keep the oxide field constant along the channel. The performance of an as-fabricated transistor is compared to an annealed transistor using an optimized high pressure deuterium anneal discussed in more detail in [10]. The pulsed method reveals several characteristics not seen with commercial equipment like SMUs with time resolution in the ms range. ...

Electron mobility in thin In0.53Ga0.47As channel
  • Citing Conference Paper
  • September 2017

... Confined geometry transistors ensure excellent electrostatics, only at the expense of increased R TH very close to the heat source. Furthermore, new high-mobility channels (i.e., SiGe, Ge) [13][14][15][16] and high-K gate dielectrics (i.e., HfO 2 ) [17,18] have been developed to increase on-current at lower voltage and to reduce gate leakage, respectively. Unfortunately, high mobility and high-K materials have lower thermal conductivities (κ), which further increase channel R TH (∼κ − 1 ). ...

High performance and record subthreshold swing demonstration in scaled RMG SiGe FinFETs with high-Ge-content channels formed by 3D condensation and a novel gate stack process
  • Citing Conference Paper
  • June 2017

... In this paper, we reported a fabrication and electrical characterization of a GAA In0.53Ga0. Figure 6a-c, respectively, benchmark g m_max vs. minimum dimension, I ON vs. L g and g m_max vs. S, in comparison to those of previously reported non-planar In x Ga 1-x As Fin or NW MOSFETs [5,14,15,[17][18][19][20][21][22][23][24][25]. Q was defined as g m_max /S, which integrates carrier transport property and electrostatic integrity, as proposed is in [26]. ...

High performance and low leakage current InGaAs-on-silicon FinFETs with 20 nm gate length
  • Citing Conference Paper
  • June 2017