Donatella Sciuto’s research while affiliated with Politecnico di Milano and other places

Quantum computing represents an exciting computing paradigm that promises to solve problems untractable for a classical computer. The main limiting factor for quantum devices is the noise impacting qubits, which hinders the superpolynomial speedup promise. Thus, although Quantum Error Correction (QEC) mechanisms are paramount, QEC demands high speed and low latency to scale quantum computations to real-life-sized problems. Within this context, hardware accelerators, such as Field Programmable Gate Arrays (FPGAs), represent a valuable approach to fulfilling QEC requirements. Nevertheless, the literature falls short in proposing solutions targeting the toric code, a type of quantum Low-Density Parity Check code capable of encoding two logical qubits, thus requiring fewer physical qubits. This manuscript presents QUEKUF , an FPGA-based QEC dataflow architecture dealing with the toric code. QUEKUF disposes of parallel processing units to spatially parallelize QEC, which a centralized controller orchestrates for data movement and operation decisions. We also provide a latency-oriented resource optimization model to identify the best theoretical configuration of QUEKUF that minimizes latency and optimizes resource requirements based upon high-level quantum parameters. Experimental results show that QUEKUF attains up to 7.30× speedup and 81.51× improvement in energy efficiency over a C++ implementation with error-free syndromes while keeping high accuracy.

Quantum computing is a new paradigm of computation that exploits principles from quantum mechanics to achieve an exponential speedup compared to classical logic. However, noise strongly limits current quantum hardware, reducing achievable performance and limiting the scaling of the applications. For this reason, current noisy intermediate-scale quantum devices require Quantum Error Correction (QEC) mechanisms to identify errors occurring in the computation and correct them in real time. Nevertheless, the high computational complexity of QEC algorithms is incompatible with the tight time constraints of quantum devices. Thus, hardware acceleration is paramount to achieving real-time QEC. This work presents QASBA, an FPGA-based hardware accelerator for the Sparse Blossom Algorithm (SBA), a state-of-the-art decoding algorithm. After profiling the state-of-the-art software counterpart, we developed a design methodology for hardware development based on the SBA. We also devised an automation process to help users without expertise in hardware design in deploying architectures based on QASBA. We implement QASBA on different FPGA architectures and experimentally evaluate resource usage, execution time, and energy efficiency of our solution. Our solution attains up to 25.05× speedup and 304.16× improvement in energy efficiency compared to the software baseline.

Blockchain technology has the potential to transform the gaming industry by enabling players to own in-game assets and receive NFTs or tokens as rewards for their accomplishments. However, one critical issue is determining how to ensure that achievement conditions are met (e.g., that the player completed level number ten). Current approaches either open cheating backdoors (e.g. if the client checks the conditions) or introduce centralization points and limitations (if a backend checks the condition). To overcome these problems a potential solution may seem to execute games directly on-chain, but the high computational cost (especially on Ethereum) and latency has made it impossible so far; however, the development of new technologies like proofs of computation enables new approaches. In this paper we employ succint proofs of computation to allow the player to prove to a smart contract on a blockchain that he reached (achieved) a certain state in an action game, that can then be played directly in the client; this allows to implement decentralized systems that can ensure fair and transparent rewarding. Moreover, we address the problem of proving that a certain game on the client has taken no more than a specific amount of time.

This paper explores software updates for Internet of Things (IoT) and Edge devices, focusing on the concept of device ownership. Our analysis of existing solutions reveals that, although asymmetric cryptography addresses the basic security and authenticity challenges of updates, it lacks flexibility in supporting a wide range of conditions or protocols, such as those needed for owner delegation and revocation of update privileges. As a potential solution, we propose the use of smart contracts on blockchain technology to articulate control policies, utilizing the blockchain’s decentralization, security, and Turing-complete expressiveness for managing firmware updates. Additionally, we investigate how IoT devices with limited resources can interact with the blockchain, initially through a gateway model deployed on an ESP32 architecture, and subsequently via a direct connection by proposing a light consensus node for more capable architectures like the ARM Cortex-A72. Our findings suggest that smart contracts offer a viable and innovative method for firmware update control, presenting new opportunities for secure, efficient, and adaptable device management in IoT and Edge computing environments.