Deepika Ahlawat’s scientific contributions

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Publications (2)

Performance Analysis of Verilog Directed Testbench vs Constrained Random SystemVerilog Testbench
  • Article

May 2015

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42 Reads

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2 Citations

International Journal of Computer Applications

Deepika Ahlawat

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Neeraj Kr. Shukla
Fig. 1. SPI Architecture [7]  
Fig. 2. Verification Flow [8]
Fig. 3. Architectural overview of the verification modules as implemented in the proposed verification environment V. DESIGN SIMULATION  
Fig. 7. Output Waveform of SPI Core
Fig. 8. Coverage report based on assertion 2) Total Coverage Percentage Total coverage here (figure 9) includes both the assertion based coverage and the functional coverage. The functional coverage is based on the coverpoints of the corresponding covergroup. Bins have been created and have been hit properly to generate functional coverage.  

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DUT Verification Through an Efficient and Reusable Environment with Optimum Assertion and Functional Coverage in SystemVerilog
  • Article
  • Full-text available

May 2014

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908 Reads

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4 Citations

International Journal of Advanced Computer Science and Applications

Deepika Ahlawat

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Neeraj Kr

Verification is the most integral part of chip manufacturing and testing and is as important as the designing. Verification provides with the actual implementation and functionality of a Design under Test (DUT) and checks if it meets the specifications or not. In this paper, a communication protocol has been verified as per the design specifications. The environment so created completely wraps the design under verification and observes an optimum functional and assertion based coverage. The coverage so obtained is 100% assertion based coverage and 83.3% functional coverage using SV (SystemVerilog). The total coverage so obtained is 91.66%.

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