David P. Nackashi’s research while affiliated with Rice University and other places

As a two-dimensional carbon nanomaterial, graphene has a high surface area and good chemical stability; therefore, its potential applicability in composite materials and as a catalyst support is high. Here, we report a facile process to decorate graphene sheets with well-dispersed Pd nanoparticles. By the in situ formation and adhesion of Pd nanoparticles to the thermally exfoliated graphene (TEG) sheets suspended in a solvent, a Pd/TEG composite was prepared and characterized by transmission electron microscopy, X-ray photoelectron spectroscopy, and Brunauer−Emmett−Teller (BET) surface area analysis. The migration and aggregation of Pd nanoparticles on the graphene sheets was directly observed by scanning transmission electron microscopy. As the composite was heated to 700 °C, there was little movement of the Pd nanoparticles; on heating to 800 °C, well below the melting temperature, the Pd nanoparticles began to migrate, coalesce, and agglomerate to form larger particles. The aggregation behavior was further confirmed by X-ray diffraction analysis of the Pd/TEG composite before and after being annealed at 800 °C. The graphene sheets provided a real-time imaging platform with nanometer-scale thickness to study the thermal stability and migratory behavior of nanoscale materials.

The electronic properties of silicon, such as the conductivity, are largely dependent on the density of the mobile charge carriers, which can be tuned by gating and impurity doping. When the device size scales down to the nanoscale, routine doping becomes problematic due to inhomogeneities. Here we report that a molecular monolayer, covalently grafted atop a silicon channel, can play a role similar to gating and impurity doping. Charge transfer occurs between the silicon and the molecules upon grafting, which can influence the surface band bending, and makes the molecules act as donors or acceptors. The partly charged end-groups of the grafted molecular layer may act as a top gate. The doping- and gating-like effects together lead to the observed controllable modulation of conductivity in pseudometal-oxide-semiconductor field-effect transistors (pseudo-MOSFETs). The molecular effects can even penetrate through a 4.92-mum thick silicon layer. Our results offer a paradigm for controlling electronic characteristics in nanodevices at the future diminutive technology nodes.

An experiment was conducted to show that the conductance of pseudo-MOSFETs can be systematically tuned, consistent with the electron-donating ability of the molecules grafted atop the oxide-free H-terminated silicon surfaces in the channel region, due to charge transfer between the device channel and the grafted molecule. The oxide-free H-terminated p- and n-channel devices were used as control samples. The pseudo-MOSFET devices were built on silicon-on-insulator (SOI) wafers. The handle layer was p-Si doped, 14-22 ω cm, 675 μm thick and acted as the back gate terminal, which was biased through a Au back contact to induce a conduction channel at the upper interface of the buried oxide (BOX). The results envisioned the new opportunities using hybrid designs not only as a new method for tuning the performance of devices but also for chemical sensors.

We have controllably modulated the drain current (I(D)) and threshold voltage (V(T)) in pseudo metal-oxide-semiconductor field-effect transistors (MOSFETs) by grafting a monolayer of molecules atop oxide-free H-passivated silicon surfaces. An electronically controlled series of molecules, from strong pi-electron donors to strong pi-electron acceptors, was covalently attached onto the channel region of the transistors. The device conductance was thus systematically tuned in accordance with the electron-donating ability of the grafted molecules, which is attributed to the charge transfer between the device channel and the molecules. This surface grafting protocol might serve as a useful method for controlling electronic characteristics in small silicon devices at future technology nodes.

Interfacing the nanoworld with the microworld represents a critical challenge to fully integrated nanosystems. Solutions to this problem have generally required either nanoprecision alignment or stochastic assembly. A design is presented that allows complete and deterministic fanout of regular arrays of wires from the nano- to the microworld without the need for any critical translational alignment steps. For example, deterministically connecting 10-nm wires directly to 3-mum wires would require a translational alignment to within only about 6 mum. The design also allows for nanowire interconnect and is independent of the technology used to fabricate the nanowires, enabling technologies for which alignment remains very challenging. The impact of potential fabrication errors is analyzed and a structure is fabricated that demonstrates the feasibility of such a design

Two efficient, physically based models for the real-time simulation of molecular device characteristics of single molecules are developed. These models assume that through-molecule tunnelling creates a steady-state Lorentzian distribution of excess electron density on the molecule and provides for smooth transitions for the electronic degrees of freedom between the tunnelling, molecular-excitation, and charge-hopping transport regimes. They are implemented in the fREEDA™ transient circuit simulator to allow for the full integration of nanoscopic molecular devices in standard packages that simulate entire devices including CMOS circuitry. Methods are presented to estimate the parameters used in the models via either direct experimental measurement or density-functional calculations. The models require 6 8 orders of magnitude less computer time than do full a priori simulations of the properties of molecular components. Consequently, molecular components can be efficiently implemented in circuit simulators. The molecular-component models are tested by comparison with experimental results reported for 1,4-benzenedithiol.

Nanoelectronic molecular and magnetic tunnel junction (MTJ) MRAM crossbar memory systems have the potential to present significant area advantages (4 to 6F(2)) compared to CMOS-based systems. The scalability of these conductivity-switched RAM arrays is examined by establishing criteria for correct functionality based on the readout margin. Using a combined circuit theoretical modelling and simulation approach, the impact of both the device and interconnect architecture on the scalability of a conductivity-state memory system is quantified. This establishes criteria showing the conditions and on/off ratios for the large-scale integration of molecular devices, guiding molecular device design. With 10% readout margin on the resistive load, a memory device needs to have an on/off ratio of at least 7 to be integrated into a 64 x 64 array, while an on/off ratio of 43 is necessary to scale the memory to 512 x 512.

Many two terminal molecular devices functioning as diodes have been synthesized with responses similar to solid state devices such as rectifying and resonant tunneling diodes. In this paper, the feasibility of integrating these molecular diodes into current circuit architectures is explored. A bistable latch and memory architecture are simulated using IV data from the 2'-amino-4-ethynylphenyl-4'-ethynylphenyl-5'-nitro-1-bensenethiolate molecule previously published by the Reed group at Yale University. HSPICE simulation results are used to illustrate the performance of a bistable latch and a memory array.

We have demonstrated a new planar edge defined alternate layer (PEDAL) process to make sub-25 nm nanowires across the whole wafer. The PEDAL process is useful in the fabrication of metal nanowires directly onto the wafer by shadow metallization and has the ability to fabricate sub-10 nm nanowires with 20 nm pitch. The process can also be used to make templates for the nano-imprinting with which the crossbar structures can be fabricated. The process involves defining the edge by etching a trench patterned by conventional i-line lithography, followed by deposition of alternating layers of silicon nitride and crystallized a-Si. The thickness of these layers determines the width and spacing of the nanowires. Later the stack is planarized to the edge of the trench by spinning polymer Shipley 1813 and then dry etching the polymer, nitride and polysilicon stack with non-selective RIE etch recipe. Selective wet etch of either nitride or polysilicon gives us the array of an aligned nanowires template. After shadow metallization of the required metal, we get metal nanowires on the wafer. The process has the flexibility of routing the nanowires around the logic and memory modules all across the wafer. The fabrication facilities required for the process are readily available and this process provides the great alternative to existing slow and/or costly nanowire patterning techniques. (P.D. Franzon).

A novel masking technique that enables the complex patterning of metal on any layer of a released MEMS chip is demonstrated. This technique enables a polysilicon only MEMS process to create low-loss RF devices. To illustrate the advantages of post-release metallization, in a polysilicon only MEMS process, a rotating MEMS tunable capacitor that provides a wide and linear tuning range is presented. The core of the design comes from high yield, mechanically proven gear designs from Sandia"s SUMMiT design library. Significant alterations were made to the gear structure to create the final device. Preliminary tests show device capacitance ratios of 1.8:1, with linear tuning. Increased metal deposition to reduce the device air gap, can produce a capacitance ratio over 6:1.